【EDA】APB_BUS总线接口Verilog及testbench

[{"title":"（ 17 个子文件 19KB ） 【EDA】APB_BUS总线接口Verilog及testbench","children":[{"title":"APB_BUS","children":[{"title":"APB_BUS.qws <span style='color:#111;'> 1.21KB </span>","children":null,"spread":false},{"title":"db","children":[{"title":"APB_BUS.map.qmsg <span style='color:#111;'> 7.93KB </span>","children":null,"spread":false},{"title":"prev_cmp_APB_BUS.qmsg <span style='color:#111;'> 7.93KB </span>","children":null,"spread":false},{"title":"APB_BUS.hif <span style='color:#111;'> 176B </span>","children":null,"spread":false},{"title":"APB_BUS.sld_design_entry.sci <span style='color:#111;'> 223B </span>","children":null,"spread":false},{"title":"APB_BUS.db_info <span style='color:#111;'> 140B </span>","children":null,"spread":false},{"title":"APB_BUS.cbx.xml <span style='color:#111;'> 89B </span>","children":null,"spread":false},{"title":"APB_BUS.cmp.rdb <span style='color:#111;'> 3.93KB </span>","children":null,"spread":false},{"title":"APB_BUS.map.rdb <span style='color:#111;'> 1.11KB </span>","children":null,"spread":false}],"spread":true},{"title":"APB_BUS.qsf <span style='color:#111;'> 2.49KB </span>","children":null,"spread":false},{"title":"APB_BUS.v <span style='color:#111;'> 758B </span>","children":null,"spread":false},{"title":"APB_BUS.qpf <span style='color:#111;'> 1.28KB </span>","children":null,"spread":false},{"title":"APB_BUS.v.bak <span style='color:#111;'> 826B </span>","children":null,"spread":false},{"title":"output_files","children":[{"title":"APB_BUS.map.rpt <span style='color:#111;'> 16.72KB </span>","children":null,"spread":false},{"title":"APB_BUS.map.summary <span style='color:#111;'> 537B </span>","children":null,"spread":false},{"title":"APB_BUS.map.smsg <span style='color:#111;'> 177B </span>","children":null,"spread":false},{"title":"APB_BUS.flow.rpt <span style='color:#111;'> 6.16KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]