FPGAVerlog实现简单CPU(可烧录及小脚丫)

上传者: ABCyvxuan | 上传时间: 2023-12-19 15:24:01 | 文件大小: 74.39MB | 文件类型: ZIP
该资源利用Verlog实现了简单CPU,并可烧录进小脚丫进行验证,资源包内附有演示视频,大家可以观看整个演示过程,也可根据视频烧录进自己的小脚丫进行验证。另外详细设计请参考本人的博客【FPGA】设计一个简单CPU—Verlog实现。希望可以帮助到大家。

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