library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vgacore is Port ( clk : in std_logic; reset : in std_logic; md : in std_logic_vector(1 downto 0); hs : out std_logic; vs : out std_logic; r : out std_logic_vector(1 downto 0); g : out std_logic_vector(2 downto 0); b : out std_logic_vector(2 downto 0) ); end vgacore;

针对VGA分配器因电路复杂、基色信号放大不平衡、信号波反射等引起的图像偏色、拖尾、重影等缺陷,在分析了CMOS反相器的电压传输特性曲线的基础上,设计了一种VGA信号多路分配电路。该电路采用CMOS反相器作为模拟小信号放大电路,由74HCU04AP集成电路构成R、G、B三基色放大电路通道,由射极跟随电路驱动信号输出,能提供4路以上独立的75Ω负载输出,实现一路VGA信号输入、多路VGA信号输出的功能。实际应用表明,该电路结构简单、成本低廉、可靠性高。

实战篇\_VGA图片显示实验（基于ROM）ppt,实战篇_VGA图片显示实验（基于ROM）

想着在此基础上通过 VGA显示器显示一张图片， 利用 FPGA 内部 ROM 存储图片数据，然后通过控制读取数据地址将图片数据传给 VGA驱动模块，从而将每个图片数据显示在对应的像素点上。

定昌电子 dc_rk3399_VGA 的armbian固件 接口正常 完美适配

嵌入式linux系统开发，LCD驱动开发程序。基于FrameBuffer的底层驱动开发

分析 EDID 的小工具 生成如下形式的说明文档： Adr Value Remark Description 00h 00h 01h FFh 02h FFh 03h FFh 04h FFh 05h FFh 06h FFh 07h 00h 08h 34h MAG EISA Manufacturer ID (high) 09h 27h EISA Manufacturer ID (low) 0Ah 17h 0717h EISA Product ID(low) 0Bh 07h EISA Product ID(high) 0Ch 02h 2 Serial Number 0Dh 00h Serial Number 0Eh 00h Serial Number 0Fh 00h Serial Number 10h 0Dh 13 Week of Manufacture 11h 0Eh 2004 Year of Manufacture 12h 01h 1 EDID Version 13h 03h 3 EDID Revision 14h 08h Video Input Definition Bit 7 : 0 = Analog signal Bit 6,5: 00 = 0.700,0.300(1.000Vpp) Bit 4 : 0 = No blank-to-black setup Bit 3 : 1 = Separate sync supported Bit 2 : 0 = No composite sync supported Bit 1 : 0 = No sync on green supported Bit 0 : 0 = No serration of the Vsync required 15h 22h 34 Max. Horizontal Image Size 16h 1Bh 27 Max. Vertical Image Size 17h 96h 2.5 Display Transfer Characteristic (Gamma) 18h 28h Feature Support (DPMS) Bit 7 : 0 = No stand-by mode Bit 6 : 0 = No suspend mode Bit 5 : 1 = Active off Bit 4,3: 01 = R/G/B color display Bit 2 : 0 = No standard default color space Bit 1 : 0 = No preferred timing mode Bit 0 : 0 = No GTF supported 19h 67h Red / Green Low Bits 1Ah 55h Blue/ White Low Bits 1Bh A5h 0.646 Red X 1Ch 5Bh 0.357 Red X 1Dh 47h 0.278 Green X 1Eh 9Ch 0.612 Green Y 1Fh 25h 0.146 Blue X 20h 1Eh 0.118 Blue Y 21h 4Fh 0.31 White X 22h 54h 0.329 White Y 23h BFh Established Timings 1 Bit 7 : 1 = 720 x 400 : 70 Hz Bit 6 : 0 Bit 5 : 1 = 640 x 480 : 60 Hz Bit 4 : 1 = 640 x 480 : 67 Hz Bit 3 : 1 = 640 x 480 : 72 Hz Bit 2 : 1 = 640 x 480 : 75 Hz Bit 1 : 1 = 800 x 600 : 56 Hz Bit 0 : 1 = 800 x 600 : 60 Hz 24h EFh Established Timings 2 Bit 7 : 1 = 800 x 600 : 72 Hz Bit 6 : 1 = 800 x 600 : 75 Hz Bit 5 : 1 = 832 x 624 : 75 Hz Bit 4 : 0 Bit 3 : 1 = 1024 x 768 : 60 Hz Bit 2 : 1 = 1024 x 768 : 70 Hz Bit 1 : 1 = 1024 x 768 : 75 Hz Bit 0 : 1 = 1280 x1024 : 75 Hz 25h 00h Manufacturers Timings 26h 31h 640 x 480 27h 40h 60 Hz 28h 45h 800 x 600 29h 40h 60 Hz 2Ah 61h 1024 x 768 2Bh 40h 60 Hz 2Ch 81h 1280 x 1024 2Dh 80h 60 Hz 2Eh 31h 640 x 480 2Fh 4Fh 75 Hz 30h 45h 800 x 600 31h 4Fh 75 Hz 32h 61h 1024 x 768 33h 4Fh 75 Hz 34h 81h 1280 x 1024 35h 8Fh 75 Hz 36h 30h 108Mhz Pixel Clock (low) 37h 2Ah Pixel Clock (high) 38h 00h 1280 Horizontal Active (low) 39h 98h 408 Horizontal Blank (low) 3Ah 51h H.Active/H.Blank (high) 3Bh 00h 1024 Vertikal Active (low) 3Ch 2Ah 42 Vertikal Blank (low) 3Dh 40h V.Active/V.Blank (high) 3Eh 30h 48 H.Front Porch (low) 3Fh 70h 112 H.Sync Pulse Width (low) 40h 13h 1/3 V.Front Porch/V.Sync PW (low) 41h 00h H/V Sync (high) 42h 51h 337 H.Image Size (low) 43h 0Eh 270 V.Image Size (low) 44h 11h H/V Smage Size (high) 45h 00h 0 H.Border 46h 00h 0 H.Border 47h 1Eh Flags 48h 00h Flag = 0000h 49h 00h 4Ah 00h Reserved = 00h 4Bh FFh Tag=Monitor S/N String 4Ch 00h Flag = 00h 4Dh 31h '1' 4Eh 0Ah 4Fh 20h 50h 20h 51h 20h 52h 20h 53h 20h 54h 20h 55h 20h 56h 20h 57h 20h 58h 20h 59h 20h 5Ah 00h Flag = 0000h 5Bh 00h 5Ch 00h Reserved = 00h 5Dh FCh Monitor Name 5Eh 00h Flag = 00h 5Fh 50h 'P' 60h 53h 'S' 61h 2Dh '-' 62h 37h '7' 63h 37h '7' 64h 36h '6' 65h 49h 'I' 66h 0Ah 67h 20h 68h 20h 69h 20h 6Ah 20h 6Bh 20h 6Ch 00h Flag = 0000h 6Dh 00h 6Eh 00h Reserved = 00h 6Fh FDh Tag=Monitor Range Limits 70h 00h Flag = 00h 71h 3Ch 60 Min. vert. Frequency [Hz] 72h 4Bh 75 Max. vert. Frequency [Hz] 73h 1Eh 30 Min. hor. Frequency [kHz] 74h 50h 80 Max. hor. Frequency [kHz] 75h 0Eh 140 Max. Pixel Frequency [MHz/10] 76h 00h Reserved for VESA GTF (=00) 77h 0Ah Set to 0Ah 78h 20h 79h 20h 7Ah 20h 7Bh 20h 7Ch 20h 7Dh 20h 7Eh 00h EDID Ext. Flag 7Fh 15h Checksum

基于FPGA的VGA图形显示

proteus仿真，输入一段音频，初级放大之后到AD603增益可变放大器放大，然后通过峰峰值检测电路检测峰峰值，和标准峰峰值电压对比，反馈到AD603进行增益调节，实现恒峰峰值放大（增益可变电路）（效果不是很好，经供参考）

Y430_WIN7_NV_VGA.exe