Quartus_II_13.1破解器.zip x86 Quartus_II_13.1破解器.zip x86
2021-08-20 12:08:34
71KB
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基于Verilog HDL的全功能UART IP核的设计与实习.基于Verilog HDL的全功能UART IP核的设计与实习.
2021-08-12 17:55:34
238KB
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用matlab设计50阶的滤波器，得出抽头系数，在Altera的EP4C10F17C8平台中实现，添加了AD/DA的代码，可直接在开发板中实现，也可以用Modelsim中仿真
2021-08-01 13:05:16
7.21MB
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QuartusII_13.0下载地址
Quartus II Subscription Edition Software DVD
http://download.altera.com/akdlm/software/acdsinst/13.0/156/iso/Quartus-13.0.0.156-windows.iso
Quartus II Device Package 1 DVD
http://download.altera.com/akdlm/software/acdsinst/13.0/156/iso/Quartus-13.0.0.156-devices-1.iso
Quartus II Device Package 2 DVD
http://download.altera.com/akdlm/software/acdsinst/13.0/156/iso/Quartus-13.0.0.156-devices-2.iso
破解时注意：当有多个网卡时license.dat里的XXXXXXXXXXXX 用第一个网卡号(NIC ID)替换
2021-07-31 14:49:07
27KB
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Error: Current license file does not support the EP2C5T144C8 device 此类错误是因为破解不完全，用这个软件工具可以完全破解！
2021-07-29 11:38:35
17KB
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该资源是基于VHDL语言在Quartus平台上实现全加器的设计
采用顶层和底层的设计 底层的半加器用VHDL或者原理图来实现
2021-07-08 17:52:30
834KB
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