Simple AES/Rijndael IP Core. I have tried to create a implementation of this
standard that would fit in to a low cost FPGA, like the Spartan IIe series from Xilinx,
and still would provide reasonably fast performance.
This implementation is with a 128 bit key expansion module only. Implementations
with different key sizes (192 & 256 bits) and performance parameters (such
as a fully pipelined ultra-high -speed version) are commercially available from
ASICS.ws (www.asics.ws).
This document will describe the interface to the IP core. It will not talk about
the AES standard itself.
2021-11-22 07:25:46
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