This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
2019-12-21 21:23:51
4.37MB
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Linux 版本的RTL8111/8168B PCI EXPRESS网卡驱动。。。
2019-12-21 20:04:51
unknown
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PCI Express Card Electromechanical Specification Revision 3.0；
PCIE CEM 3.0标准；
PCI Express Add-In Card、Mother Board标准规范。
2019-12-21 19:59:34
3.1MB
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PCI Express® Card Electromechanical Specification Revision 3.0
2019-12-21 19:48:02
1.37MB
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PCI Express Mini CEM 2.0 Specification是目前最新的MINI-PCI-E协议，PCI-E-MINI
2019-12-21 19:30:07
888KB
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PCI Express 3.0 is the latest generation of the popular peripheral interface found in virtually every PC, server, and industrial computer. Its high bandwidth, low latency, and cost-to-performance ratio make it a natural choice for many peripheral devices today. Each new generation of PCI Express adds more features, capabilities and bandwidth, which maintains its popularity as a device interconnect.
MindShare's books take the hard work out of deciphering the specs, and this one follows that tradition. MindShare's PCI Express Technology book provides a thorough description of the interface with numerous practical examples that illustrate the concepts. Written in a tutorial style, this book is ideal for anyone new to PCI Express. At the same time, its thorough coverage of the details makes it an essential resource for seasoned veterans.
主要内容如下：
PCI Express Origins
Configuration Space and Access Methods
Enumeration Process
Packet Types and Fields
Transaction Ordering
Traffic Classes, Virtual Channels and Arbitration (QoS)
Flow Control
ACK/NAK Protocol
Logical PHY (8b/10b, 128b/130b, Scrambling)
Electrical PHY
Link Training and Initialization
Interrupt Delivery (Legacy, MSI, MSI-X)
Error Detection and Reporting
Power Management (for both software and hardware)
2.0 and 2.1 Features (such as 5.0GT/s, TLP Hints, and Multi-Casting)
3.0 Features (such as 8.0GT/s, and a new encoding scheme)
Considerations for High Speed Signaling (such as Equalization)
2019-11-19 21:16:53
47.38MB
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