最新版A55 软件优化文档 V3
The Cortex-A55 core is a mid-range, low-power core that implements the Armv8-A architecture with support for the Armv8.1-A
extension, the Armv8.2-A extension, the RAS extension, the Load acquire (LDAPR) instructions introduced in the Armv8.3-A
extension, and the Dot Product instructions introduced in the Armv8.4-A extension.
All pipelines within the Cortex-A55 core have been designed to be optimal with both the AArch32 and AArch64 instruction sets.
There is no bias towards one or other instruction set.
This document describes elements of the Cortex-A55 micro-architecture that influence software performance so that software and
compilers can be optimized accordingly
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