随着技术的迅速发展，越来越多的工程应用对以太网嵌入式设备提出了需求，因此对以太网MAC层数据处理系统的研究具有重要的现实意义。本文介绍利用以太网物理层（PHY）芯片和FPGA实现的硬件千兆网模块。其中PHY芯片作为数据传输的高速节点，处理物理层数据，而FPGA完成对MAC层数据的处理。本文研究的方法结合了FPGA的强大处理能力和PHY 芯片的驱动能力，比常规CPU+MAC层模块+PHY芯片的方式有更高的效率。本文通过实验测试验证了设计的可靠性与快速性。

This document describes the usage of the TJA1100 Customer Evaluation Board. The Board supports the evaluation of the TJA1100 with providing (MII) a 40-pins standard header (including MII/SMI/control signals/power supplies. Details can be found in section 2.3.1) with 2,54mm pinning distance to a host controller board, the bus interface (MDI) including a srew terminal (SMKDS) connector as well as needed components for the power supply and operation. Further information is given in the following sections.

The TJA1101B is a 100BASE-T1-compliant Ethernet PHY optimized for automotive use cases such as gateways, IP camera links, radar modules, driver assistance systems and back-bone networks. The device provides 100 Mbit/s transmit and receive capability over a single unshielded twisted-pair cable, supporting a cable length of up to at least 15 m. The TJA1101B has been designed for automotive robustness and ISO 26262, ASIL-A compliance, while minimizing power consumption and system costs.

This reference document describes the configuration, register structure and mapping of the TJA1101A Ethernet PHY.

个人写的LINUX平台下，命令行访问ethernet phy 的寄存器工具，驱动和硬件调试非常实用。具体使用如下： 打印寄存器：./mdio eth0 dump 修改寄存器：./mdio eth0 0x00 0x1200，修改0x00寄存器的值为0x1200

The Alaska® 88E1510/88E1518/88E1512/88E1514 device is a physical layer device containing a single 10/100/1000 Gigabit Ethernet transceiver. The transceiver implements the Ethernet physical layer portion of the 1000BASE-T, 100BASE-TX, and 10BASE-T standards.

mipi_D-PHY_specification

有关不同的phy接口 architecture，pcie，sata，usb3.0

USB 3.0 PHY spec for designing PHY. It's similar to SATA II and PCIe GEN2 specification

City College of the City University of the New York的Jianliang Zheng提供了NS2的IEE 802.15.4（zigbee）脚本，源程序和文档等。由于Zheng的个人主页已经登不上，所以上传到scdn上供需要的人使用。