win7 sp1+USB3.0+NVME+UEFI.iso

WINDOWS系统下刷写BIOS的工具。

System Management BIOS (SMBIOS) Reference 6 Specification 7 Supersedes: 3.1.1 8 Document Class: Normative 9 Document Status: Published 10 Document Language: en-US 11System Management BIOS (SMBIOS) Reference Specification DSP0134 2 Published Version 3.2.0 12 Copyright Notice 13 Copyright © 2000, 2002, 2004–2016 Distributed Management Task Force, Inc. (DMTF). All rights 14 reserved. 15 DMTF is a not-for-profit association of industry members dedicated to promoting enterprise and systems 16 management and interoperability. Members and non-members may reproduce DMTF specifications and 17 documents, provided that correct attribution is given. As DMTF specifications may be revised from time to 18 time, the particular version and release date should always be noted. 19 Implementation of certain elements of this standard or proposed standard may be subject to third party 20 patent rights, including provisional patent rights (herein "patent rights"). DMTF makes no representations 21 to users of the standard as to the existence of such rights, and is not responsible to recognize, disclose, 22 or identify any or all such third party patent right, owners or claimants, nor for any incomplete or 23 inaccurate identification or disclosure of such rights, owners or claimants. DMTF shall have no liability to 24 any party, in any manner or circumstance, under any legal theory whatsoever, for failure to recognize, 25 disclose, or identify any such third party patent rights, or for such party’s reliance on the standard or 26 incorporation thereof in its product, protocols or testing procedures. DMTF shall have no liability to any 27 party implementing such standard, whether such implementation is foreseeable or not, nor to any patent 28 owner or claimant, and shall have no liability or responsibility for costs or losses incurred if a standard is 29 withdrawn or modified after publication, and shall be indemnified and held harmless by any party 30 implementing the standard from any and all claims of infringement by a patent owner for such 31 implementations. 32 For information about patents held by third-parties which have notified the DMTF that, in their opinion, 33 such patent may relate to or impact implementations of DMTF standards, visit 34 http://www.dmtf.org/about/policies/disclosures.php. 35 This document’s normative language is English. Translation into other languages is permitted.DSP0134 System Management BIOS (SMBIOS) Reference Specification Version 3.2.0 Published 3 36 CONTENTS 37 Foreword ....................................................................................................................................................... 9 38 Introduction.................................................................................................................................................. 10 39 Document conventions........................................................................................................................ 10 40 Typographical conventions ....................................................................................................... 10 41 Document version number conventions ................................................................................... 10 42 1 Scope .................................................................................................................................................. 13 43 1.1 Supported processor architectures........................................................................................... 13 44 2 Normative references .......................................................................................................................... 13 45 3 Terms and definitions .......................................................................................................................... 15 46 4 Symbols and abbreviated terms.......................................................................................................... 15 47 5 Accessing SMBIOS information .......................................................................................................... 21 48 5.1 General ..................................................................................................................................... 21 49 5.2 Table convention....................................................................................................................... 21 50 5.2.1 SMBIOS 2.1 (32-bit) Entry Point.................................................................................. 22 51 5.2.2 SMBIOS 3.0 (64-bit) Entry Point.................................................................................. 23 52 6 SMBIOS structures.............................................................................................................................. 24 53 6.1 Structure standards................................................................................................................... 24 54 6.1.1 Structure evolution and usage guidelines.................................................................... 25 55 6.1.2 Structure header format............................................................................................... 26 56 6.1.3 Text strings .................................................................................................................. 26 57 6.2 Required structures and data ................................................................................................... 27 58 6.3 SMBIOS fields and CIM MOF properties.................................................................................. 28 59 7 Structure definitions............................................................................................................................. 29 60 7.1 BIOS Information (Type 0)........................................................................................................ 29 61 7.1.1 BIOS Characteristics.................................................................................................... 31 62 7.1.2 BIOS Characteristics Extension Bytes......................................................................... 32 63 7.2 System Information (Type 1) .................................................................................................... 33 64 7.2.1 System — UUID........................................................................................................... 34 65 7.2.2 System — Wake-up Type............................................................................................ 35 66 7.3 Baseboard (or Module) Information (Type 2) ........................................................................... 35 67 7.3.1 Baseboard — feature flags .......................................................................................... 36 68 7.3.2 Baseboard — Board Type ........................................................................................... 37 69 7.4 System Enclosure or Chassis (Type 3) .................................................................................... 37 70 7.4.1 System Enclosure or Chassis Types........................................................................... 39 71 7.4.2 System Enclosure or Chassis States........................................................................... 40 72 7.4.3 System Enclosure or Chassis Security Status ............................................................ 41 73 7.4.4 System Enclosure or Chassis — Contained Elements................................................ 41 74 7.5 Processor Information (Type 4) ................................................................................................ 42 75 7.5.1 Processor Information — Processor Type................................................................... 45 76 7.5.2 Processor Information — Processor Family ................................................................ 46 77 7.5.3 Processor ID field format ............................................................................................. 52 78 7.5.4 Processor Information — Voltage................................................................................ 52 79 7.5.5 Processor Information — Processor Upgrade............................................................. 53 80 7.5.6 Processor Information — Core Count.......................................................................... 55 81 7.5.7 Processor Information — Core Enabled...................................................................... 55 82 7.5.8 Processor Information — Thread Count...................................................................... 56 83 7.5.9 Processor Characteristics............................................................................................ 56 84 7.6 Memory Controller Information (Type 5, Obsolete) .................................................................. 57 85 7.6.1 Memory Controller Error Detecting Method................................................................. 58 86 7.6.2 Memory Controller Error Correcting Capability............................................................ 58 87 7.6.3 Memory Controller Information — Interleave Support................................................. 58System Management BIOS (SMBIOS) Reference Specification DSP0134 4 Published Version 3.2.0 88 7.6.4 Memory Controller Information — Memory Speeds .................................................... 59 89 7.7 Memory Module Information (Type 6, Obsolete) ...................................................................... 59 90 7.7.1 Memory Module Information — Memory Types .......................................................... 60 91 7.7.2 Memory Module Information — Memory Size ............................................................. 60 92 7.7.3 Memory subsystem example ....................................................................................... 61 93 7.8 Cache Information (Type 7) ...................................................................................................... 63 94 7.8.1 Cache Information — Maximum Cache Size and Installed Size ................................. 65 95 7.8.2 Cache Information — SRAM Type .............................................................................. 65 96 7.8.3 Cache Information — Error Correction Type ............................................................... 66 97 7.8.4 Cache Information — System Cache Type ................................................................. 66 98 7.8.5 Cache Information — Associativity.............................................................................. 66 99 7.9 Port Connector Information (Type 8) ........................................................................................ 67 100 7.9.1 Port Information example............................................................................................. 68 101 7.9.2 Port Information — Connector Types .......................................................................... 68 102 7.9.3 Port Types.................................................................................................................... 69 103 7.10 System Slots (Type 9)............................................................................................................... 70 104 7.10.1 System Slots — Slot Type ........................................................................................... 71 105 7.10.2 System Slots — Slot Data Bus Width.......................................................................... 73 106 7.10.3 System Slots — Current Usage................................................................................... 74 107 7.10.4 System Slots — Slot Length ........................................................................................ 74 108 7.10.5 System Slots — Slot ID ............................................................................................... 74 109 7.10.6 Slot Characteristics 1................................................................................................... 75 110 7.10.7 Slot Characteristics 2................................................................................................... 75 111 7.10.8 Segment Group Number, Bus Number, Device/Func

统一可扩展固件接口(UEFI)规范描述了操作系统和平台固件之间的接口。UEFI之前是可扩展固件接口规范1.10 (EFI)。因此，一些代码和某些协议名称保留了EFI名称。除非另有说明，本规范中的EFI名称可能被认为是UEFI的一部分。 接口采用数据表的形式，其中包含与平台相关的信息，以及OS加载器和OS可用的引导和运行时服务调用。它们共同提供了一个引导操作系统的标准环境。本规范是作为一个纯粹的接口规范设计的。因此，该规范定义了平台固件必须实现的接口和结构集。类似地，该规范定义了操作系统在引导时可能使用的一组接口和结构。固件开发人员如何选择实现所需的元素，或者操作系统开发人员如何选择利用这些接口和结构，这是留给开发人员的实现决策。 该规范的目的是定义一种方法，使操作系统和平台固件仅通信支持操作系统引导过程所必需的信息。这是通过平台和固件提供给操作系统的软件可见接口的正式和完整的抽象规范来实现的。 使用这一正式定义，旨在运行在与受支持的处理器规范兼容的平台上的收缩包装操作系统将能够在各种系统设计上启动，而无需进一步的平台或操作系统定制。该定义还允许平台创新引入新特性和功能，以增强平台的能力，而不需要按照操作系统的引导顺序编写新代码。 此外，抽象规范开辟了一条替代遗留设备和固件代码的路径。新的设备类型和相关代码可以通过相同定义的抽象接口提供同等的功能，同样不会影响OS引导支持代码。 该规范适用于从移动系统到服务器的所有硬件平台。该规范提供了一组核心服务以及一组协议接口。协议接口的选择可以随着时间的推移而发展，并针对不同的平台市场细分进行优化。与此同时，该规范允许oem提供最大限度的可扩展性和定制能力，以实现差异化。在这方面，UEFI的目的是定义一个从传统的“PC-AT”风格的引导世界到一个没有遗留api的环境的进化路径。

uefi新手，入门程序

uefi开发的标准，此文档是硬件引导uefi开发的标准，uefi对硬件环境进行检测。

Windows UEFI Shell,UEFI引导可用

本文详细解释了基于linux redhat 7.5操作系统搭建的pxe+kickstart（UEFI）网络安装server服务器的配置步骤和方法，其中包含一些kickstart文件的解释，以及可直接使用的kickstart文件配置。文章末尾还有楼主邮箱哟，如部署出现问题可随时联系我~

X86平台qemu支持UEFI引导的固件。

This Unified Extensible Firmware Interface (hereafter known as UEFI) Specification describes an interface between the operating system (OS) and the platform firmware. UEFI was preceded by the Extensible Firmware Interface Specification 1.10 (EFI). As a result, some code and certain protocol names retain the EFI designation. Unless otherwise noted, EFI designations in this specification may be assumed to be part of UEFI. The interface is in the form of data tables that contain platform-related information, and boot and runtime service calls that are available to the OS loader and the OS. Together, these provide a standard environment for booting an OS. This specification is designed as a pure interface specification. As such, the specification defines the set of interfaces and structures that platform firmware must implement. Similarly, the specification defines the set of interfaces and structures that the OS may use in booting. How either the firmware developer chooses to implement the required elements or the OS developer chooses to make use of those interfaces and structures is an implementation decision left for the developer. The intent of this specification is to define a way for the OS and platform firmware to communicate only information necessary to support the OS boot process. This is accomplished through a formal and complete abstract specification of the software-visible interface presented to the OS by the platform and firmware. Using this formal definition, a shrink-wrap OS intended to run on platforms compatible with supported processor specifications will be able to boot on a variety of system designs without further platform or OS customization. The definition will also allow for platform innovation to introduce new features and functionality that enhance platform capability without requiring new code to be written in the OS boot sequence. Furthermore, an abstract specification opens a route to replace legacy devices and firmwa