详细介绍一个支持15条指令的MIPS CPU设计过程

"1_TO_4 " contains the following sections. 1 VERILOG Examples This section contains the VERILOG examples of Chapter 11 of the book. It supports computer aided searching and own simulations. 2 Interpreter Model This is the complete VERILOG model of the RISC processor TOOBSIE on the behavior level. It serves as a reference for the instruction set. 3 Coarse Structure Model This is the complete VERILOG model of the RISC processor TOOBSIE on the register transfer level and below. 4 Operating System and Examples The operating system VOS supports more comfortable experiments with the Coarse Structure Model. For this purpose, there are also example application programs. This section, however, does not belong to the actual target of the book. "5VWELDOS.ZIP" and "6VWELSUN.ZIP" contain the VERILOG simulator VeriWell for the PC under MS-DOS and the SUN Sparc under UNIX, respectively, as well as our first hints "5_0READ.1ST" and "6_0READ.1ST", respectively, followed by the documentation of the supplier of VeriWell.