FPGA读取模数转换芯片AD7606数据并波形显示例程Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, input[15:0] ad7606_data, //ad7606 data input ad7606_busy, //ad7606 busy input ad7606_first_data, //ad7606 first data output[2:0] ad7606_os, //ad7606 output ad7606_cs, //ad7606 AD cs output ad7606_rd, //ad7606 AD data read output ad7606_reset, //ad7606 AD reset output ad7606_convstab, //ad7606 AD convert start //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue ); wire video_clk; wire video_hs; wire video_vs; wire video_de; wire[7:0] video_r; wire[7:0] video_g; wire[7:0] video_b; wire grid_hs; wire grid_vs; wire grid_de; wire[7:0] grid_r; wire[7:0] grid_g; wire[7:0] grid_b; wire wave0_hs; wire wave0_vs; wire wave0_de; wire[7:0] wave0_r; wire[7:0] wave0_g; wire[7:0] wave0_b; wire wave1_hs; wire wave1_vs; wire