KEY_4x4扫描键盘FPGAVerilog逻辑源码Quartus工程文件,FPGA为CYCLONE4系列中的EP4CE6E22C8. 完整的工程文件,可以做为你的学习设计参考。
module KEY_4x4
(
input sys_clk, //50MHZ
input sys_rst_n ,
input [3:0] key_row , //��
//output wire [3:0] key_col , //��
output reg [3:0] key_col , //��
output wire [7:0] LED , //��ʾ��ֵ
output reg [3:0] key_value //��ֵ
);
reg [5:0] count;//delay_20ms
reg [2:0] state; //״̬��־
reg key_flag; //������־λ
reg clk_500khz; //500KHZʱ���ź�
reg [3:0] key_col_reg; //�Ĵ�ɨ����ֵ
reg [3:0] key_row_reg; //�Ĵ�ɨ����ֵ
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
clk_500khz <= 0 ;
count= 50 ) begin
clk_500khz <= ~clk_500khz ;
count<=0;
end
else
count <= count + 1;
end
end
always @(posedge clk_500khz or negedge sys_rst_n)
if(!sys_rst_n) begin
key_col<=4'b0000;
state<=0;
end
else
begin
case (state)
0:
begin
key_col[3:0]<=4'b0000;
key_flag<=1'b0;
if(key_row[3:0]!=4'b1111) begin //�м����£�ɨ����һ��
state<=1;
key_col[3:0]<=4'b1110;
end
else
state<=0;
end
1:
begin
if(key_row[3:0]!=4'b1111) //�ж��Ƿ��ǵ�һ��
state<=5;
else begin
state<=2;
key_col[3:0]<=4'b1101; //ɨ���ڶ���
end
end
2:
begin
if(key_row[3:0]!=4'b1111) //�ж��Ƿ��ǵڶ���
state<=5;
else begin //ɨ��������
state<=3;
key_col[3:0]<=4'b1011;
end
end
3:
begin
if(key_row[3:0]!=4'b1111) //�ж��Ƿ��ǵ���һ��
state<=5;
else begin
state<=4;
key_col[3:0]<=4'b0111;
end //ɨ��������
end
4:
begin
if (key_row