上传者: zhaowy2008
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上传时间: 2021-12-20 15:23:20
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文件大小: 629KB
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文件类型: -
The goal of the MyHDL project is to empower hardware designers with the elegance and
simplicity of the Python language.
MyHDL is a free, open-source package for using Python as a hardware description and verification language. Python is a very high level language, and hardware designers can use its
full power to model and simulate their designs. Moreover, MyHDL can convert a design to
Verilog or VHDL. This provides a path into a traditional design flow.