数字均衡器的FPGA实现(VHDL)

上传者: zhaotian1573 | 上传时间: 2021-08-22 15:23:24 | 文件大小: 75KB | 文件类型: RAR
数字均衡器的FPGA实现(VHDL),数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用

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评论信息

  • shewdooo :
    很完整的代码 还是不错
    2013-12-23
  • u010679089 :
    很有用,很完整,非常感谢分享
    2013-10-31
  • wq_huang :
    加入工程后,综合还有很多错识,不过均是VHDL源代码,有一定的参考价值,但注释太少,不容看懂
    2013-07-29
  • shuiyuanyuhe :
    跑一下试试,VHDL源代码,不知道支不支持CYLONEIII。
    2013-07-18
  • feiyuzhuxian :
    还不错,比较完整,有一定的参考价值,感谢分享
    2013-07-01

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