基于fpga的Aurora接口控制代码（streaming）

[{"title":"（ 89 个子文件 29.45MB ） 基于fpga的Aurora接口控制代码（streaming）","children":[{"title":"Aurora_InFac_Framing - 副本","children":[{"title":"IPAuroraProc_Rx_Fifo","children":[{"title":"IPAuroraProc_Rx_Fifo","children":[{"title":"IPAuroraProc_Rx_Fifo.xdc <span style='color:#111;'> 2.79KB </span>","children":null,"spread":false},{"title":"IPAuroraProc_Rx_Fifo_clocks.xdc <span style='color:#111;'> 3.36KB </span>","children":null,"spread":false}],"spread":true},{"title":"IPAuroraProc_Rx_Fifo.xci <span style='color:#111;'> 54.93KB </span>","children":null,"spread":false},{"title":"IPAuroraProc_Rx_Fifo.vho <span style='color:#111;'> 3.55KB </span>","children":null,"spread":false},{"title":"IPAuroraProc_Rx_Fifo_sim_netlist.v <span style='color:#111;'> 148.16KB </span>","children":null,"spread":false},{"title":"synth","children":[{"title":"IPAuroraProc_Rx_Fifo.vhd <span style='color:#111;'> 38.19KB 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style='color:#111;'> 106.58KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_1_1","children":[{"title":"simulation","children":[{"title":"fifo_generator_vlog_beh.v <span style='color:#111;'> 433.78KB </span>","children":null,"spread":false}],"spread":false},{"title":"hdl","children":[{"title":"fifo_generator_v13_1_rfs.vhd <span style='color:#111;'> 1.33MB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_1_vhsyn_rfs.vhd <span style='color:#111;'> 2.22MB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_1.vhd <span style='color:#111;'> 89.05KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_1_rfs.v <span style='color:#111;'> 581.57KB </span>","children":null,"spread":false}],"spread":false}],"spread":false},{"title":"blk_mem_gen_v8_3_3","children":[{"title":"hdl","children":[{"title":"blk_mem_gen_v8_3_vhsyn_rfs.vhd <span style='color:#111;'> 14.14MB </span>","children":null,"spread":false},{"title":"blk_mem_gen_v8_3.vhd <span style='color:#111;'> 20.98KB </span>","children":null,"spread":false}],"spread":false}],"spread":false},{"title":"IPAuroraProc_Rx_Fifo_ooc.xdc <span style='color:#111;'> 2.45KB </span>","children":null,"spread":false}],"spread":false},{"title":"IPAuroraProc_Tx_Fifo","children":[{"title":"IPAuroraProc_Tx_Fifo","children":[{"title":"IPAuroraProc_Tx_Fifo.xdc <span style='color:#111;'> 2.79KB </span>","children":null,"spread":false},{"title":"IPAuroraProc_Tx_Fifo_clocks.xdc <span style='color:#111;'> 3.36KB </span>","children":null,"spread":false}],"spread":true},{"title":"IPAuroraProc_Tx_Fifo_stub.vhdl <span style='color:#111;'> 1.65KB </span>","children":null,"spread":false},{"title":"IPAuroraProc_Tx_Fifo.xci <span style='color:#111;'> 54.93KB </span>","children":null,"spread":false},{"title":"synth","children":[{"title":"IPAuroraProc_Tx_Fifo.vhd <span style='color:#111;'> 38.19KB </span>","children":null,"spread":false}],"spread":true},{"title":"doc","children":[{"title":"fifo_generator_v13_1_changelog.txt <span style='color:#111;'> 7.36KB </span>","children":null,"spread":false}],"spread":true},{"title":"IPAuroraProc_Tx_Fifo.vho <span style='color:#111;'> 3.55KB </span>","children":null,"spread":false},{"title":"IPAuroraProc_Tx_Fifo_stub.v <span style='color:#111;'> 1.53KB </span>","children":null,"spread":false},{"title":"IPAuroraProc_Tx_Fifo.xml <span style='color:#111;'> 546.16KB </span>","children":null,"spread":false},{"title":"IPAuroraProc_Tx_Fifo_ooc.xdc <span style='color:#111;'> 2.45KB </span>","children":null,"spread":false},{"title":"sim","children":[{"title":"IPAuroraProc_Tx_Fifo.v <span style='color:#111;'> 14.61KB </span>","children":null,"spread":false}],"spread":true},{"title":"IPAuroraProc_Tx_Fifo.veo <span style='color:#111;'> 3.26KB </span>","children":null,"spread":false},{"title":"IPAuroraProc_Tx_Fifo_sim_netlist.vhdl <span style='color:#111;'> 213.67KB </span>","children":null,"spread":false},{"title":"IPAuroraProc_Tx_Fifo.dcp <span style='color:#111;'> 106.40KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_1_1","children":[{"title":"simulation","children":[{"title":"fifo_generator_vlog_beh.v <span style='color:#111;'> 433.78KB </span>","children":null,"spread":false}],"spread":false},{"title":"hdl","children":[{"title":"fifo_generator_v13_1_rfs.vhd <span style='color:#111;'> 1.33MB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_1_vhsyn_rfs.vhd <span style='color:#111;'> 2.22MB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_1.vhd <span style='color:#111;'> 89.05KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_1_rfs.v <span style='color:#111;'> 581.57KB </span>","children":null,"spread":false}],"spread":false}],"spread":false},{"title":"blk_mem_gen_v8_3_3","children":[{"title":"hdl","children":[{"title":"blk_mem_gen_v8_3_vhsyn_rfs.vhd <span style='color:#111;'> 14.14MB </span>","children":null,"spread":false},{"title":"blk_mem_gen_v8_3.vhd <span style='color:#111;'> 20.98KB </span>","children":null,"spread":false}],"spread":false}],"spread":false},{"title":"IPAuroraProc_Tx_Fifo_sim_netlist.v <span style='color:#111;'> 148.16KB </span>","children":null,"spread":false}],"spread":false},{"title":"aurora_8b10b_0_CLOCK_MODULE.v <span style='color:#111;'> 4.43KB </span>","children":null,"spread":false},{"title":"Gtx_Comm_Wrapper.v <span style='color:#111;'> 6.91KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_axi_to_ll_exdes.v <span style='color:#111;'> 6.38KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_SUPPORT_RESET_LOGIC.v <span style='color:#111;'> 6.23KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_ll_to_axi_exdes.v <span style='color:#111;'> 5.56KB </span>","children":null,"spread":false},{"title":"Aurora_Rest_Pro.v <span style='color:#111;'> 2.09KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0","children":[{"title":"aurora_8b10b_0.v <span style='color:#111;'> 7.67KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_stub.vhdl <span style='color:#111;'> 3.00KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_sim_netlist.vhdl <span style='color:#111;'> 673.09KB </span>","children":null,"spread":false},{"title":"doc","children":[{"title":"aurora_8b10b_v11_0_changelog.txt <span style='color:#111;'> 9.01KB </span>","children":null,"spread":false}],"spread":true},{"title":"aurora_8b10b_0_stub.v <span style='color:#111;'> 3.00KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_sim_netlist.v <span style='color:#111;'> 491.75KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0","children":[{"title":"gt","children":[{"title":"aurora_8b10b_0_gt.v <span style='color:#111;'> 44.55KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_tx_startup_fsm.v <span style='color:#111;'> 25.43KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_rx_startup_fsm.v <span style='color:#111;'> 33.63KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_transceiver_wrapper.v <span style='color:#111;'> 27.14KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_multi_gt.v <span style='color:#111;'> 16.86KB </span>","children":null,"spread":false}],"spread":false},{"title":"src","children":[{"title":"aurora_8b10b_0_sym_gen.v <span style='color:#111;'> 11.76KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_aurora_lane.v <span style='color:#111;'> 11.60KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_channel_init_sm.v <span style='color:#111;'> 11.38KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_rx_stream.v <span style='color:#111;'> 4.08KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_chbond_count_dec.v <span style='color:#111;'> 3.34KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_ll_to_axi.v <span style='color:#111;'> 5.51KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_reset_logic.v <span style='color:#111;'> 7.96KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_tx_stream.v <span style='color:#111;'> 6.48KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_global_logic.v <span style='color:#111;'> 5.78KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_err_detect.v <span style='color:#111;'> 9.17KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_idle_and_ver_gen.v <span style='color:#111;'> 11.83KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_standard_cc_module.v <span style='color:#111;'> 11.83KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_lane_init_sm.v <span style='color:#111;'> 18.48KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_cdc_sync.v <span style='color:#111;'> 17.95KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_sym_dec.v <span style='color:#111;'> 18.38KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_hotplug.v <span style='color:#111;'> 7.20KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_axi_to_ll.v <span style='color:#111;'> 6.30KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_channel_err_detect.v <span style='color:#111;'> 5.31KB </span>","children":null,"spread":false}],"spread":false}],"spread":false},{"title":"aurora_8b10b_0.vho <span style='color:#111;'> 5.68KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0.xml <span style='color:#111;'> 2.22MB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_clocks.xdc <span style='color:#111;'> 3.28KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0.xci <span style='color:#111;'> 27.37KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0.veo <span style='color:#111;'> 5.94KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0.dcp <span style='color:#111;'> 269.95KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_ooc.xdc <span style='color:#111;'> 3.26KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_core.v <span style='color:#111;'> 21.36KB </span>","children":null,"spread":false}],"spread":false},{"title":"Aurora_IntFac.v <span style='color:#111;'> 16.75KB </span>","children":null,"spread":false},{"title":"aurora_8b10b_0_cdc_sync_exdes.v <span style='color:#111;'> 17.95KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]