经典8位RISC-CPU设计(附testbench)

上传者: zackzhaoyang | 上传时间: 2019-12-21 22:16:35 | 文件大小: 435KB | 文件类型: rar
采用哈佛结构设计的简单8位RISC-CPU,包含testbench,可直接在modelsim中出波形。是《Verilog HDL程序设计实例详解》中的8位RISC-CPU的源码,亲测可用!

文件下载

资源详情

[{"title":"( 65 个子文件 435KB ) 经典8位RISC-CPU设计(附testbench)","children":[{"title":"risc8","children":[{"title":"cpu_test.v <span style='color:#111;'> 12.80KB </span>","children":null,"spread":false},{"title":"risc8.mpf <span style='color:#111;'> 18.41KB </span>","children":null,"spread":false},{"title":"dram.v <span style='color:#111;'> 331B </span>","children":null,"spread":false},{"title":"transcript <span style='color:#111;'> 338B </span>","children":null,"spread":false},{"title":"risc8.vcd <span style='color:#111;'> 1.17MB </span>","children":null,"spread":false},{"title":"idec.v <span style='color:#111;'> 4.28KB </span>","children":null,"spread":false},{"title":"pram.v <span style='color:#111;'> 460B </span>","children":null,"spread":false},{"title":"sindata.hex <span style='color:#111;'> 8.00KB </span>","children":null,"spread":false},{"title":"chart","children":[{"title":"图13-7.bmp <span style='color:#111;'> 357.64KB </span>","children":null,"spread":false},{"title":"图13-18.bmp <span style='color:#111;'> 402.12KB </span>","children":null,"spread":false},{"title":"表13-1.bmp <span style='color:#111;'> 432.90KB </span>","children":null,"spread":false},{"title":"图13-20.bmp <span style='color:#111;'> 615.99KB </span>","children":null,"spread":false},{"title":"图13-11.bmp <span style='color:#111;'> 444.90KB </span>","children":null,"spread":false},{"title":"图13-16.bmp <span style='color:#111;'> 272.09KB </span>","children":null,"spread":false},{"title":"图13-9.bmp <span style='color:#111;'> 444.90KB </span>","children":null,"spread":false},{"title":"图13-6.bmp <span style='color:#111;'> 357.64KB </span>","children":null,"spread":false},{"title":"图13-13.bmp <span style='color:#111;'> 366.98KB </span>","children":null,"spread":false},{"title":"图13-17.bmp <span style='color:#111;'> 357.64KB </span>","children":null,"spread":false},{"title":"图13-15.bmp <span style='color:#111;'> 272.09KB </span>","children":null,"spread":false},{"title":"Thumbs.db <span style='color:#111;'> 31.50KB </span>","children":null,"spread":false}],"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 80.00KB </span>","children":null,"spread":false},{"title":"work","children":[{"title":"dram","children":[{"title":"_primary.vhd <span style='color:#111;'> 416B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 4.78KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 384B </span>","children":null,"spread":false}],"spread":true},{"title":"regs","children":[{"title":"_primary.vhd <span style='color:#111;'> 504B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 7.55KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.49KB </span>","children":null,"spread":false}],"spread":true},{"title":"_info <span style='color:#111;'> 1.48KB </span>","children":null,"spread":false},{"title":"exp","children":[{"title":"_primary.vhd <span style='color:#111;'> 502B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 8.67KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.34KB </span>","children":null,"spread":false}],"spread":false},{"title":"risc8.vcd <span style='color:#111;'> 1.17MB </span>","children":null,"spread":false},{"title":"cpu","children":[{"title":"_primary.vhd <span style='color:#111;'> 2.10KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 75.27KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 12.85KB </span>","children":null,"spread":false}],"spread":false},{"title":"pram","children":[{"title":"_primary.vhd <span style='color:#111;'> 421B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 5.37KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 462B </span>","children":null,"spread":false}],"spread":false},{"title":"alu","children":[{"title":"_primary.vhd <span style='color:#111;'> 838B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 13.59KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.40KB </span>","children":null,"spread":false}],"spread":false},{"title":"cpu_test","children":[{"title":"_primary.vhd <span style='color:#111;'> 1.49KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 82.88KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 8.97KB </span>","children":null,"spread":false}],"spread":false},{"title":"test","children":[{"title":"_primary.vhd <span style='color:#111;'> 1.48KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 82.88KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 8.97KB </span>","children":null,"spread":false}],"spread":false},{"title":"idec","children":[{"title":"_primary.vhd <span style='color:#111;'> 634B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 9.84KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 3.83KB </span>","children":null,"spread":false}],"spread":false}],"spread":false},{"title":"cpu.v <span style='color:#111;'> 15.45KB </span>","children":null,"spread":false},{"title":"risc8.cr.mti <span style='color:#111;'> 1.72KB </span>","children":null,"spread":false},{"title":"regs.v <span style='color:#111;'> 1.49KB </span>","children":null,"spread":false},{"title":"alu.v <span style='color:#111;'> 1.37KB </span>","children":null,"spread":false},{"title":"exp.v <span style='color:#111;'> 1.80KB </span>","children":null,"spread":false},{"title":"basic.rom <span style='color:#111;'> 2.23KB </span>","children":null,"spread":false},{"title":"wave","children":[{"title":"cpu_test.bmp <span style='color:#111;'> 1.59MB </span>","children":null,"spread":false},{"title":"regs.bmp <span style='color:#111;'> 1.02MB </span>","children":null,"spread":false},{"title":"exp.bmp <span style='color:#111;'> 1.20MB </span>","children":null,"spread":false},{"title":"idec.bmp <span style='color:#111;'> 1.19MB </span>","children":null,"spread":false},{"title":"alu.bmp <span style='color:#111;'> 1008.74KB </span>","children":null,"spread":false},{"title":"cpu-2.bmp <span style='color:#111;'> 2.32MB </span>","children":null,"spread":false},{"title":"pram.bmp <span style='color:#111;'> 889.51KB </span>","children":null,"spread":false},{"title":"cpu-1.bmp <span style='color:#111;'> 2.58MB </span>","children":null,"spread":false},{"title":"Thumbs.db <span style='color:#111;'> 24.00KB </span>","children":null,"spread":false}],"spread":false}],"spread":false}],"spread":true}]

评论信息

  • wp_zhong :
    是modelsim仿真
    2017-05-23
  • zwp221 :
    是modelsim仿真
    2017-05-23
  • schspa :
    很好,直接就是modelsim仿真的,,
    2014-07-25
  • schspa :
    很好,直接就是modelsim仿真的,,
    2014-07-25
  • u014706926 :
    比较有用的资料,
    2014-05-08
  • 尘恩cj :
    比较有用的资料,
    2014-05-08
  • zhangkang_123 :
    对项目有些用
    2013-12-26
  • zhangkang_123 :
    对项目有些用
    2013-12-26
  • shiweianquan :
    很实用,毕业设计靠他l
    2013-12-07
  • shiweianquan :
    很实用,毕业设计靠他l
    2013-12-07

免责申明

【只为小站】的资源来自网友分享,仅供学习研究,请务必在下载后24小时内给予删除,不得用于其他任何用途,否则后果自负。基于互联网的特殊性,【只为小站】 无法对用户传输的作品、信息、内容的权属或合法性、合规性、真实性、科学性、完整权、有效性等进行实质审查;无论 【只为小站】 经营者是否已进行审查,用户均应自行承担因其传输的作品、信息、内容而可能或已经产生的侵权或权属纠纷等法律责任。
本站所有资源不代表本站的观点或立场,基于网友分享,根据中国法律《信息网络传播权保护条例》第二十二条之规定,若资源存在侵权或相关问题请联系本站客服人员,zhiweidada#qq.com,请把#换成@,本站将给予最大的支持与配合,做到及时反馈和处理。关于更多版权及免责申明参见 版权及免责申明