基于FPGA用verilogHDL设计的DES加密模块

[{"title":"（ 9 个子文件 4KB ） 基于FPGA用verilogHDL设计的DES加密模块","children":[{"title":"des_encoder.v <span style='color:#111;'> 10.67KB </span>","children":null,"spread":false},{"title":"sbox2.txt <span style='color:#111;'> 216B </span>","children":null,"spread":false},{"title":"sbox7.txt <span style='color:#111;'> 216B </span>","children":null,"spread":false},{"title":"sbox5.txt <span style='color:#111;'> 215B </span>","children":null,"spread":false},{"title":"sbox8.txt <span style='color:#111;'> 216B </span>","children":null,"spread":false},{"title":"sbox4.txt <span style='color:#111;'> 213B </span>","children":null,"spread":false},{"title":"sbox3.txt <span style='color:#111;'> 215B </span>","children":null,"spread":false},{"title":"sbox6.txt <span style='color:#111;'> 216B </span>","children":null,"spread":false},{"title":"sbox1.txt <span style='color:#111;'> 216B </span>","children":null,"spread":false}],"spread":true}]