时序设计与约束资料

[{"title":"（ 12 个子文件 10.13MB ） 时序设计与约束资料","children":[{"title":"时序设计与约束资料","children":[{"title":"系统时序基础理论.pdf <span style='color:#111;'> 364.51KB </span>","children":null,"spread":false},{"title":"关于maoci的讨论和可靠性有关的几个概念.doc <span style='color:#111;'> 88.00KB </span>","children":null,"spread":false},{"title":"静态时序分析（Static Timing Analysis）基础与应用.pdf <span style='color:#111;'> 984.51KB </span>","children":null,"spread":false},{"title":"时序分析之3优化策略.pdf <span style='color:#111;'> 3.06MB </span>","children":null,"spread":false},{"title":"华为静态时序分析与逻辑设计.pdf <span style='color:#111;'> 956.13KB </span>","children":null,"spread":false},{"title":"时序分析之1静态分析基础.pdf <span style='color:#111;'> 687.10KB </span>","children":null,"spread":false},{"title":"同步电路设计中CLOCK SKEW的分析.doc <span style='color:#111;'> 179.50KB </span>","children":null,"spread":false},{"title":"时序分析之2Timequest教程.pdf <span style='color:#111;'> 4.61MB </span>","children":null,"spread":false},{"title":"大型设计中FPGA 的多时钟设计策略.pdf <span style='color:#111;'> 210.83KB </span>","children":null,"spread":false},{"title":"经典时序.pdf <span style='color:#111;'> 295.67KB </span>","children":null,"spread":false},{"title":"Xilinx公司对高速PCB信号的优化设计.pdf <span style='color:#111;'> 606.89KB </span>","children":null,"spread":false},{"title":"Xilinx_constraints.pdf <span style='color:#111;'> 1.42MB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]