经典中的经典！ic前端几本经典书籍（五本书全部到齐）

[{"title":"（ 30 个子文件 109.68MB ） 经典中的经典！ic前端几本经典书籍（五本书全部到齐）","children":[{"title":"经典中的经典！ic前端几本经典书籍（五本书全部到齐！！）","children":[{"title":"RTL Validation设计的宝典书籍.rar <span style='color:#111;'> 5.52MB </span>","children":null,"spread":false},{"title":"VHDL以及Verilog 设计的宝典书籍","children":[{"title":"样品BOM——小批量低价BOM表分析工具.url <span style='color:#111;'> 135B </span>","children":null,"spread":false},{"title":"A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.pdf <span style='color:#111;'> 38.75MB </span>","children":null,"spread":false},{"title":"张飞1-20.jpg <span style='color:#111;'> 4.34MB </span>","children":null,"spread":false},{"title":"免费申请领取样品.url <span style='color:#111;'> 140B </span>","children":null,"spread":false},{"title":"新建 文本文档.txt <span style='color:#111;'> 162B </span>","children":null,"spread":false}],"spread":true},{"title":"详细讲述了在IC DESIGN FLOW中.rar <span style='color:#111;'> 5.30MB </span>","children":null,"spread":false},{"title":"SOCIP可重用设计","children":[{"title":"样品BOM——小批量低价BOM表分析工具.url <span style='color:#111;'> 135B </span>","children":null,"spread":false},{"title":"张飞1-20.jpg <span style='color:#111;'> 4.34MB </span>","children":null,"spread":false},{"title":"Reuse.Methodology.Manual.3rd.Edition.pdf <span style='color:#111;'> 6.42MB </span>","children":null,"spread":false},{"title":"免费申请领取样品.url <span style='color:#111;'> 140B </span>","children":null,"spread":false},{"title":"新建 文本文档.txt <span style='color:#111;'> 155B </span>","children":null,"spread":false}],"spread":true},{"title":"RTL Validation设计的宝典书籍","children":[{"title":"(Kluwer) Writing Testbenches--Functional Verification of HDL Models.pdf <span style='color:#111;'> 5.69MB </span>","children":null,"spread":false},{"title":"样品BOM——小批量低价BOM表分析工具.url <span style='color:#111;'> 135B </span>","children":null,"spread":false},{"title":"张飞1-20.jpg <span style='color:#111;'> 4.34MB </span>","children":null,"spread":false},{"title":"免费申请领取样品.url <span style='color:#111;'> 140B </span>","children":null,"spread":false},{"title":"新建 文本文档.txt <span style='color:#111;'> 215B </span>","children":null,"spread":false}],"spread":true},{"title":"主流IC设计","children":[{"title":"样品BOM——小批量低价BOM表分析工具.url <span style='color:#111;'> 135B </span>","children":null,"spread":false},{"title":"张飞1-20.jpg <span style='color:#111;'> 4.34MB </span>","children":null,"spread":false},{"title":"免费申请领取样品.url <span style='color:#111;'> 140B </span>","children":null,"spread":false},{"title":"Advanced.ASIC.Chip.Synthesis.2nd.Edition.pdf <span style='color:#111;'> 15.23MB </span>","children":null,"spread":false},{"title":"新建 文本文档.txt <span style='color:#111;'> 251B </span>","children":null,"spread":false}],"spread":true},{"title":"SOCIP可重用设计.rar <span style='color:#111;'> 5.95MB </span>","children":null,"spread":false},{"title":"主流IC设计.rar <span style='color:#111;'> 5.45MB </span>","children":null,"spread":false},{"title":"详细讲述了在IC DESIGN FLOW中","children":[{"title":"样品BOM——小批量低价BOM表分析工具.url <span style='color:#111;'> 135B </span>","children":null,"spread":false},{"title":"张飞1-20.jpg <span style='color:#111;'> 4.34MB </span>","children":null,"spread":false},{"title":"免费申请领取样品.url <span style='color:#111;'> 140B </span>","children":null,"spread":false},{"title":"详细讲述了在IC DESIGN FLOW中.txt <span style='color:#111;'> 180B </span>","children":null,"spread":false},{"title":"(Kluwer) Principles of Verifiable RTL Design (2nd Ed.).pdf <span style='color:#111;'> 3.94MB </span>","children":null,"spread":false}],"spread":true},{"title":"VHDL以及Verilog 设计的宝典书籍.rar <span style='color:#111;'> 32.61MB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]