使用转换函数 (Conversion Functions) 解决类型不匹配问题

上传者: xyl903481310 | 上传时间: 2021-03-18 11:10:15 | 文件大小: 204KB | 文件类型: ZIP
# 目的是掌握IEEE的转换功能。 numeric_std软件包(请参阅提供的文件“ VHDL_1164pkg.pdf”)来解决 VHDL。 # Describe in behavioral VHDL a modulo-m up/down counter with the following interface: – Generics • Modulo base (m with default value of 16) – Inputs • Clock (clk -> 1 bit) • Asynchronous reset (rst -> 1 bit) • Counting direction (up_down -> 1 bit) – 1 -> Counting up, – 0 -> Counting down – Outputs • Count value (count -> [log2(m)] bits) # The mod-m up/down counter should work as follows: – When counting up (up_down = '1'), it starts from 0, 1, 2, ..., m-1 (e.g., when m = 27 as in the provided testbench, then it should count 0, 1, 2, ..., 26 and then loops back to 0, 1, and so on) – When counting down (up_down = '0'), it starts from m-1, m-2, ..., 2, 1, 0 (e.g., when m = 27 as in the provided testbench, then it should count 26, 25, ..., 2, 1, 0 and then loops back to 26, 25, and so on) # In Vivado: – Create a project – Add design and simulation source files – Run behavioral simulation – Waveform configuration

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