[{"title":"( 2 个子文件 66KB ) 在FPGACPLD中实现AD或DA的文章(英文Verilog).7z","children":[{"title":"在FPGACPLD中实现AD或DA的文章(英文Verilog)","children":[{"title":"Virtex Analog to Digital Converter.pdf <span style='color:#111;'> 48.95KB </span>","children":null,"spread":false},{"title":"Virtex Synthesizable Delta-Sigma DAC.pdf <span style='color:#111;'> 53.55KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]