[{"title":"( 2 个子文件 3KB ) verilog编写的spi master模块","children":[{"title":"spi_master.v <span style='color:#111;'> 5.30KB </span>","children":null,"spread":false},{"title":"spi_clock.v <span style='color:#111;'> 2.55KB </span>","children":null,"spread":false}],"spread":true}]