FPGA Verilog 数字闹钟

[{"title":"（ 103 个子文件 1.51MB ） FPGA Verilog 数字闹钟","children":[{"title":"tim.map.rpt <span style='color:#111;'> 28.87KB </span>","children":null,"spread":false},{"title":"tim.map.summary <span style='color:#111;'> 452B </span>","children":null,"spread":false},{"title":"tim.fit.summary <span style='color:#111;'> 589B </span>","children":null,"spread":false},{"title":"tim.map_bb.cdb <span style='color:#111;'> 746B </span>","children":null,"spread":false},{"title":"tim.eco.cdb <span style='color:#111;'> 161B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]