SHA-3 verilogHDL实现

[{"title":"（ 13 个子文件 14KB ） SHA-3 verilogHDL实现","children":[{"title":"keccak.v <span style='color:#111;'> 3.02KB </span>","children":null,"spread":false},{"title":"round2in1.v <span style='color:#111;'> 8.43KB </span>","children":null,"spread":false},{"title":"Read_Me.txt <span style='color:#111;'> 526B </span>","children":null,"spread":false},{"title":"test_padder1.v <span style='color:#111;'> 1.93KB </span>","children":null,"spread":false},{"title":"test_f_permutation.v <span style='color:#111;'> 4.76KB </span>","children":null,"spread":false},{"title":"f_permutation.v <span style='color:#111;'> 2.00KB </span>","children":null,"spread":false},{"title":"padder1.v <span style='color:#111;'> 1.14KB </span>","children":null,"spread":false},{"title":"rconst2in1.v <span style='color:#111;'> 1.70KB </span>","children":null,"spread":false},{"title":"padder.v <span style='color:#111;'> 3.00KB </span>","children":null,"spread":false},{"title":"simulation.do <span style='color:#111;'> 785B </span>","children":null,"spread":false},{"title":"test_padder.v <span style='color:#111;'> 4.75KB </span>","children":null,"spread":false},{"title":"test_keccak.v <span style='color:#111;'> 6.84KB </span>","children":null,"spread":false},{"title":"test_rconst2in1.v <span style='color:#111;'> 3.23KB </span>","children":null,"spread":false}],"spread":true}]