循环（7，3）码编码电路设计（基于quartus的代码及仿真）

[{"title":"（ 52 个子文件 81KB ） 循环（7，3）码编码电路设计（基于quartus的代码及仿真）","children":[{"title":"aa","children":[{"title":"aa.tis_db_list.ddb <span style='color:#111;'> 296B </span>","children":null,"spread":false},{"title":"aa.qpf <span style='color:#111;'> 1.25KB </span>","children":null,"spread":false},{"title":"aa.pti_db_list.ddb <span style='color:#111;'> 292B </span>","children":null,"spread":false},{"title":"aa.v.bak <span style='color:#111;'> 415B </span>","children":null,"spread":false},{"title":"aa.qsf <span style='color:#111;'> 2.99KB </span>","children":null,"spread":false},{"title":"aa.qws <span style='color:#111;'> 698B </span>","children":null,"spread":false},{"title":"simulation","children":[{"title":"qsim","children":[{"title":"aa_modelsim.xrf <span style='color:#111;'> 1.27KB </span>","children":null,"spread":false},{"title":"transcript <span style='color:#111;'> 905B </span>","children":null,"spread":false},{"title":"aa.do <span style='color:#111;'> 351B </span>","children":null,"spread":false},{"title":"aa.sft <span style='color:#111;'> 43B </span>","children":null,"spread":false},{"title":"Waveform.vwf.vt <span style='color:#111;'> 8.28KB </span>","children":null,"spread":false},{"title":"work","children":[{"title":"_info <span style='color:#111;'> 1.06KB </span>","children":null,"spread":false},{"title":"aa_vlg_check_tst","children":[{"title":"_primary.dat <span style='color:#111;'> 3.71KB </span>","children":null,"spread":false},{"title":"verilog.prw <span style='color:#111;'> 1.39KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 213B </span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'> 31.51KB </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 2.41KB </span>","children":null,"spread":false}],"spread":false},{"title":"aa_vlg_sample_tst","children":[{"title":"_primary.dat <span style='color:#111;'> 466B </span>","children":null,"spread":false},{"title":"verilog.prw <span style='color:#111;'> 304B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 258B </span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'> 5.54KB </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 599B </span>","children":null,"spread":false}],"spread":false},{"title":"aa","children":[{"title":"_primary.dat <span style='color:#111;'> 7.43KB </span>","children":null,"spread":false},{"title":"verilog.prw <span style='color:#111;'> 3.33KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 247B </span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'> 50.41KB </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 8.05KB </span>","children":null,"spread":false}],"spread":false},{"title":"_vmake <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"aa_vlg_vec_tst","children":[{"title":"_primary.dat <span style='color:#111;'> 1.30KB </span>","children":null,"spread":false},{"title":"verilog.prw <span style='color:#111;'> 783B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 88B </span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'> 10.01KB </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 1.42KB </span>","children":null,"spread":false}],"spread":false},{"title":"_temp","children":null,"spread":false}],"spread":false},{"title":"aa.vo <span style='color:#111;'> 10.86KB </span>","children":null,"spread":false},{"title":"aa.msim.vcd <span style='color:#111;'> 6.26KB </span>","children":null,"spread":false},{"title":"aa.sim.vwf <span style='color:#111;'> 11.25KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"output_files","children":[{"title":"aa.map.summary <span style='color:#111;'> 503B </span>","children":null,"spread":false},{"title":"aa.map.smsg <span style='color:#111;'> 123B </span>","children":null,"spread":false},{"title":"aa.map.rpt <span style='color:#111;'> 20.81KB </span>","children":null,"spread":false},{"title":"aa.eda.rpt <span style='color:#111;'> 6.57KB </span>","children":null,"spread":false},{"title":"aa.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"aa.flow.rpt <span style='color:#111;'> 9.29KB </span>","children":null,"spread":false}],"spread":true},{"title":"aa.v <span style='color:#111;'> 419B </span>","children":null,"spread":false},{"title":"Waveform.vwf <span style='color:#111;'> 6.14KB </span>","children":null,"spread":false},{"title":"原理图.png <span style='color:#111;'> 19.86KB </span>","children":null,"spread":false},{"title":"仿真.png <span style='color:#111;'> 11.84KB </span>","children":null,"spread":false},{"title":"incremental_db","children":[{"title":"README <span style='color:#111;'> 653B </span>","children":null,"spread":false},{"title":"compiled_partitions","children":[{"title":"aa.db_info <span style='color:#111;'> 138B </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"db","children":[{"title":"logic_util_heursitic.dat <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"aa.db_info <span style='color:#111;'> 138B </span>","children":null,"spread":false},{"title":"aa.sld_design_entry.sci <span style='color:#111;'> 198B </span>","children":null,"spread":false},{"title":"prev_cmp_aa.qmsg <span style='color:#111;'> 6.33KB </span>","children":null,"spread":false}],"spread":false}],"spread":false}],"spread":true}]