二阶数字锁相环的FPGA实现,基于Vivado2018平台

上传者: 45857378 | 上传时间: 2023-12-13 21:25:59 | 文件大小: 23.24MB | 文件类型: ZIP
内容:二阶数字锁相环的FPGA实现工程文件 仿真平台:Vivado 2018.3 各模块:数字鉴相器(乘法器+低通滤波器),环路滤波器,压控振荡器 主要使用IP核:Multiplier,FIR Compiler,dds_compiler 注:仿真时,testbench文件中,输入数据文件目录:$readmemb("D:/FPGA_Project/04_FSK_System/PllTwoOrder/din.txt", memory); 改成自己电脑对应文本文件的目录

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