FPGA实现DDS信号源（单频、线性调频）的verilog程序（可电脑端实时控制）

[{"title":"（ 399 个子文件 5.95MB ） FPGA实现DDS信号源（单频、线性调频）的verilog程序（可电脑端实时控制）","children":[{"title":"ethernet_test.ngc <span style='color:#111;'> 190.46KB </span>","children":null,"spread":false},{"title":"work.sdbl <span style='color:#111;'> 62.81KB </span>","children":null,"spread":false},{"title":"work.sdbx <span style='color:#111;'> 191B </span>","children":null,"spread":false},{"title":"tb_ax2ad_isim_beh1.wdb <span style='color:#111;'> 67.31KB </span>","children":null,"spread":false},{"title":"ethernet_test_map.mrp <span style='color:#111;'> 34.34KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]