[{"title":"( 199 个子文件 355KB ) (verilog)简化的RISC CPU设计(夏宇闻老师书上的)","children":[{"title":"ALU.v <span style='color:#111;'> 800B </span>","children":null,"spread":false},{"title":"addr_decode.v <span style='color:#111;'> 423B </span>","children":null,"spread":false},{"title":"counter.v <span style='color:#111;'> 343B </span>","children":null,"spread":false},{"title":"clk_gen.v <span style='color:#111;'> 1.38KB </span>","children":null,"spread":false},{"title":"machine.v.bak <span style='color:#111;'> 3.97KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]