[{"title":"( 2 个子文件 2KB ) ad7606-fpga-并行,ad7606并行数据读取,Verilog","children":[{"title":"ad7606_sample.v <span style='color:#111;'> 4.34KB </span>","children":null,"spread":false},{"title":"ad7606_if.v <span style='color:#111;'> 7.09KB </span>","children":null,"spread":false}],"spread":true}]