Project_Uart.zip_3V7L_fpga_further6aa_verilog

[{"title":"（ 104 个子文件 3.06MB ） Project_Uart.zip_3V7L_fpga_further6aa_verilog","children":[{"title":"Uart_Bps_Module.v <span style='color:#111;'> 2.53KB </span>","children":null,"spread":false},{"title":"Uart_Rx_Module.v <span style='color:#111;'> 5.23KB </span>","children":null,"spread":false},{"title":"Project_Uart.sta.rdb <span style='color:#111;'> 19.37KB </span>","children":null,"spread":false},{"title":"Project_Uart.(3).cnf.hdb <span style='color:#111;'> 1.32KB </span>","children":null,"spread":false},{"title":"Project_Uart.pti_db_list.ddb <span style='color:#111;'> 246B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]