FPGA_FPGA开发

[{"title":"（ 50 个子文件 1014KB ） FPGA_FPGA开发","children":[{"title":"EDA","children":[{"title":"horse_led","children":[{"title":"tcl","children":null,"spread":false},{"title":"ip","children":null,"spread":false},{"title":"src","children":[{"title":"horse_led.v <span style='color:#111;'> 706B </span>","children":null,"spread":false}],"spread":true},{"title":"sim","children":[{"title":"horse_led_tb.v <span style='color:#111;'> 531B </span>","children":null,"spread":false}],"spread":true},{"title":"prj","children":[{"title":"db","children":[{"title":"horse_led.lpc.html <span style='color:#111;'> 372B </span>","children":null,"spread":false},{"title":"horse_led.pre_map.cdb <span style='color:#111;'> 4.17KB </span>","children":null,"spread":false},{"title":"prev_cmp_horse_led.qmsg <span style='color:#111;'> 3.78KB </span>","children":null,"spread":false},{"title":"horse_led.rtlv_sg_swap.cdb <span style='color:#111;'> 208B </span>","children":null,"spread":false},{"title":"horse_led.hier_info <span style='color:#111;'> 1.37KB </span>","children":null,"spread":false},{"title":"horse_led.(0).cnf.cdb <span style='color:#111;'> 2.89KB </span>","children":null,"spread":false},{"title":"horse_led.lpc.rdb <span style='color:#111;'> 409B </span>","children":null,"spread":false},{"title":"horse_led.db_info <span style='color:#111;'> 144B </span>","children":null,"spread":false},{"title":"horse_led.sld_design_entry.sci <span style='color:#111;'> 227B </span>","children":null,"spread":false},{"title":"horse_led.map.qmsg <span style='color:#111;'> 4.39KB </span>","children":null,"spread":false},{"title":"horse_led.pre_map.hdb <span style='color:#111;'> 10.87KB </span>","children":null,"spread":false},{"title":"horse_led.cmp.rdb <span style='color:#111;'> 4.33KB </span>","children":null,"spread":false},{"title":"horse_led.lpc.txt <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"horse_led.hif <span style='color:#111;'> 493B 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</span>","children":null,"spread":false},{"title":"incremental_db","children":[{"title":"compiled_partitions","children":[{"title":"horse_led.db_info <span style='color:#111;'> 144B </span>","children":null,"spread":false}],"spread":true},{"title":"README <span style='color:#111;'> 653B </span>","children":null,"spread":false}],"spread":true},{"title":"horse_led.qsf <span style='color:#111;'> 3.82KB </span>","children":null,"spread":false},{"title":"horse_led.qpf <span style='color:#111;'> 1.29KB </span>","children":null,"spread":false},{"title":"simulation","children":[{"title":"modelsim","children":[{"title":"msim_transcript <span style='color:#111;'> 2.44KB </span>","children":null,"spread":false},{"title":"rtl_work","children":[{"title":"_lib.qdb <span style='color:#111;'> 48.00KB </span>","children":null,"spread":false},{"title":"_lib1_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.27KB </span>","children":null,"spread":false},{"title":"_lib1_0.qtl <span style='color:#111;'> 4.92KB </span>","children":null,"spread":false},{"title":"_vmake <span style='color:#111;'> 29B </span>","children":null,"spread":false},{"title":"_lib1_0.qpg <span style='color:#111;'> 16.00KB </span>","children":null,"spread":false}],"spread":false},{"title":"horse_led_run_msim_rtl_verilog.do.bak3 <span style='color:#111;'> 586B </span>","children":null,"spread":false},{"title":"horse_led_run_msim_rtl_verilog.do.bak1 <span style='color:#111;'> 586B </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 48.00KB </span>","children":null,"spread":false},{"title":"horse_led_run_msim_rtl_verilog.do.bak4 <span style='color:#111;'> 586B </span>","children":null,"spread":false},{"title":"modelsim.ini <span style='color:#111;'> 10.87KB </span>","children":null,"spread":false},{"title":"horse_led_run_msim_rtl_verilog.do.bak2 <span style='color:#111;'> 586B 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</span>","children":null,"spread":false}],"spread":true}],"spread":true}]