sm4-verilog-master.rar

[{"title":"（ 11 个子文件 11KB ） sm4-verilog-master.rar","children":[{"title":"sm4-verilog-master","children":[{"title":"RTL","children":[{"title":"one_round_for_key_exp.v <span style='color:#111;'> 1.83KB </span>","children":null,"spread":false},{"title":"sbox_replace.v <span style='color:#111;'> 8.18KB </span>","children":null,"spread":false},{"title":"transform_for_key_exp.v <span style='color:#111;'> 1.62KB </span>","children":null,"spread":false},{"title":"transform_for_encdec.v <span style='color:#111;'> 1.67KB </span>","children":null,"spread":false},{"title":"sm4_encdec.v <span style='color:#111;'> 14.71KB </span>","children":null,"spread":false},{"title":"one_round_for_encdec.v <span style='color:#111;'> 1.21KB </span>","children":null,"spread":false},{"title":"get_cki.v <span style='color:#111;'> 1.93KB </span>","children":null,"spread":false},{"title":"sm4_top.v <span style='color:#111;'> 6.75KB </span>","children":null,"spread":false},{"title":"key_expansion.v <span style='color:#111;'> 9.35KB </span>","children":null,"spread":false}],"spread":true},{"title":"TESTBENCH","children":[{"title":"tb_sm4_top.v <span style='color:#111;'> 4.74KB </span>","children":null,"spread":false},{"title":"tb_key_expansion.v <span style='color:#111;'> 5.20KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]