RISC-V
RISC-V处理器
5阶段流水线架构
硬件设计
编译和模拟要求
sudo apt-get install ghdl gtkwave
综合要求
演练
演练将vhdl转换为verilog文件 （需要使用yosys进行synthesys）
放置和布线要求
演练
模拟
“ tb_risc_abs.vhd”是架构的测试平台。
可以通过运行gtkwave risc_v_abs.vcd看到该模拟。
编译设计
运行tb_script文件，将使用ghdl分析整个体系结构的文件。
默认情况下，将在主目录中创建一个名为“ risc_v_abs.vcd”的vcd文件。
综合系统
vhdl代码使用vhd2vl在verilog文件中转换。
使用verilog文件，可以使用yosys完成yosys 。
目标FPGA平台是ICE40 ，您可以使用yosys并使用以下yosys进行更改： synth_<targ
文件下载
资源详情
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</span>","children":null,"spread":false},{"title":"Decoder2TO4.vhd <span style='color:#111;'> 518B </span>","children":null,"spread":false},{"title":"tb_ALU.vhd <span style='color:#111;'> 2.26KB </span>","children":null,"spread":false},{"title":"andBlock.vhd <span style='color:#111;'> 454B </span>","children":null,"spread":false},{"title":"ALU.vhd <span style='color:#111;'> 6.22KB </span>","children":null,"spread":false},{"title":"adderSubALUNbit.vhd <span style='color:#111;'> 950B </span>","children":null,"spread":false}],"spread":true},{"title":"FordwardingBlock","children":[{"title":"tb_FU.vhd <span style='color:#111;'> 2.23KB </span>","children":null,"spread":false},{"title":"Comparator_Nbit.vhd <span style='color:#111;'> 451B </span>","children":null,"spread":false},{"title":"ForwardingUnit.vhd <span style='color:#111;'> 2.31KB </span>","children":null,"spread":false},{"title":"GatesNet.vhd <span style='color:#111;'> 1.47KB </span>","children":null,"spread":false}],"spread":true},{"title":"FF_en.vhd <span style='color:#111;'> 429B </span>","children":null,"spread":false}],"spread":true},{"title":"Stage4","children":[{"title":"Stage4.vhd <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false}],"spread":true},{"title":"tb_script <span style='color:#111;'> 1.88KB </span>","children":null,"spread":false},{"title":"risc_v_abs.vhd <span style='color:#111;'> 10.15KB </span>","children":null,"spread":false},{"title":"README.md <span style='color:#111;'> 1.51KB </span>","children":null,"spread":false},{"title":"makeVerilog <span style='color:#111;'> 2.33KB </span>","children":null,"spread":false},{"title":"registerNbit.vhd <span style='color:#111;'> 564B </span>","children":null,"spread":false},{"title":"to_verilog","children":[{"title":"PC.v <span style='color:#111;'> 1.29KB </span>","children":null,"spread":false},{"title":"HazardDetector.v <span style='color:#111;'> 4.15KB </span>","children":null,"spread":false},{"title":"MuxSelGenerator.v <span style='color:#111;'> 1.69KB </span>","children":null,"spread":false},{"title":"risc_v.json <span style='color:#111;'> 703.58KB </span>","children":null,"spread":false},{"title":"stage1.v <span style='color:#111;'> 2.36KB </span>","children":null,"spread":false},{"title":"ALU.v <span style='color:#111;'> 5.19KB </span>","children":null,"spread":false},{"title":"sraiBlock.v <span style='color:#111;'> 8.87KB </span>","children":null,"spread":false},{"title":"registerNbit.v <span style='color:#111;'> 1.29KB </span>","children":null,"spread":false},{"title":"ff_en.v <span style='color:#111;'> 1.21KB </span>","children":null,"spread":false},{"title":"register_32_mainblock.v <span style='color:#111;'> 6.73KB </span>","children":null,"spread":false},{"title":"ImmediateGenerator.v <span style='color:#111;'> 4.02KB </span>","children":null,"spread":false},{"title":"mux32to1.v <span style='color:#111;'> 2.58KB </span>","children":null,"spread":false},{"title":"andBlock.v <span style='color:#111;'> 1.23KB </span>","children":null,"spread":false},{"title":"Comparator_Nbit.v <span style='color:#111;'> 1.30KB </span>","children":null,"spread":false},{"title":"FormatDetector.v <span style='color:#111;'> 1.77KB </span>","children":null,"spread":false},{"title":"GatesNet.v <span style='color:#111;'> 2.48KB </span>","children":null,"spread":false},{"title":"register_nbit_clock_n.v <span style='color:#111;'> 1.33KB </span>","children":null,"spread":false},{"title":"mux4to1.v <span style='color:#111;'> 1.43KB </span>","children":null,"spread":false},{"title":"mux4to1_1bit.v <span style='color:#111;'> 1.37KB </span>","children":null,"spread":false},{"title":"adderSubNbit.v <span style='color:#111;'> 1.13KB </span>","children":null,"spread":false},{"title":"incrementerBlock.v <span style='color:#111;'> 1.44KB </span>","children":null,"spread":false},{"title":"dec5to32.v <span style='color:#111;'> 2.61KB </span>","children":null,"spread":false},{"title":"dec3to8.v <span style='color:#111;'> 1.71KB </span>","children":null,"spread":false},{"title":"dec2to4.v <span style='color:#111;'> 1.46KB </span>","children":null,"spread":false},{"title":".ff_env <span style='color:#111;'> 1.25KB </span>","children":null,"spread":false},{"title":"mux_8_to_1.v <span style='color:#111;'> 1.74KB </span>","children":null,"spread":false},{"title":"stage2.v <span style='color:#111;'> 8.54KB </span>","children":null,"spread":false},{"title":"xorBlock.v <span style='color:#111;'> 1.23KB </span>","children":null,"spread":false},{"title":"adderSubALUNbit.v <span style='color:#111;'> 1.70KB </span>","children":null,"spread":false},{"title":"incrementerSubBlock.v <span style='color:#111;'> 1.14KB </span>","children":null,"spread":false},{"title":"ControlUnit.v <span style='color:#111;'> 4.96KB </span>","children":null,"spread":false},{"title":"risc_v_abs.v <span style='color:#111;'> 5.25KB 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本站所有资源不代表本站的观点或立场，基于网友分享，根据中国法律《信息网络传播权保护条例》第二十二条之规定，若资源存在侵权或相关问题请联系本站客服人员，zhiweidada#qq.com，请把#换成@，本站将给予最大的支持与配合，做到及时反馈和处理。关于更多版权及免责申明参见 版权及免责申明