MIPS_CPU_2015:32位MIPS CPU，Verilog HDL，2015年夏季，清华大学电子工程系

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4.25KB </span>","children":null,"spread":false},{"title":"ALUController.v <span style='color:#111;'> 3.88KB </span>","children":null,"spread":false},{"title":"ALUController.v <span style='color:#111;'> 3.79KB </span>","children":null,"spread":false},{"title":"Peripheral.v <span style='color:#111;'> 3.65KB </span>","children":null,"spread":false},{"title":"Peripheral.v <span style='color:#111;'> 3.65KB </span>","children":null,"spread":false},{"title":"ID_EX_reg.v <span style='color:#111;'> 2.99KB </span>","children":null,"spread":false},{"title":"uart_tx.v <span style='color:#111;'> 2.68KB </span>","children":null,"spread":false},{"title":"uart_tx.v <span style='color:#111;'> 2.68KB </span>","children":null,"spread":false},{"title":"uart_rx.v <span style='color:#111;'> 2.60KB </span>","children":null,"spread":false},{"title":"uart_rx.v <span style='color:#111;'> 2.60KB </span>","children":null,"spread":false},{"title":"Controller.v <span style='color:#111;'> 2.42KB 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744B </span>","children":null,"spread":false},{"title":"ARITH.v <span style='color:#111;'> 744B </span>","children":null,"spread":false},{"title":"ARITH.v <span style='color:#111;'> 744B </span>","children":null,"spread":false},{"title":"CMP.v <span style='color:#111;'> 730B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]