[{"title":"( 13 个子文件 440KB ) hdl-pretty:用于美化 VHDL 和 Verilog 文件的脚本","children":[{"title":"hdl-pretty-master","children":[{"title":"LICENSE <span style='color:#111;'> 11.09KB </span>","children":null,"spread":false},{"title":"vhdl-mode","children":[{"title":"vhdl-mode.el <span style='color:#111;'> 679.98KB </span>","children":null,"spread":false},{"title":"site-start.el <span style='color:#111;'> 408B </span>","children":null,"spread":false},{"title":"vhdl-mode.info <span style='color:#111;'> 40.89KB </span>","children":null,"spread":false},{"title":"vhdl-mode.elc <span style='color:#111;'> 541.21KB </span>","children":null,"spread":false},{"title":"ChangeLog <span style='color:#111;'> 45.93KB </span>","children":null,"spread":false},{"title":"INSTALL <span style='color:#111;'> 3.73KB </span>","children":null,"spread":false},{"title":"README <span style='color:#111;'> 834B </span>","children":null,"spread":false}],"spread":true},{"title":"README.md <span style='color:#111;'> 701B </span>","children":null,"spread":false},{"title":"vindent.el <span style='color:#111;'> 931B </span>","children":null,"spread":false},{"title":"vhdl-pretty <span style='color:#111;'> 1.74KB </span>","children":null,"spread":false},{"title":"verilog-pretty <span style='color:#111;'> 1.75KB </span>","children":null,"spread":false},{"title":"macs-verilog-mode","children":[{"title":"verilog-mode.el <span style='color:#111;'> 523.12KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]