riscv-simple-sv:一个简单的RISC V核心教学-源码

上传者: 42101164 | 上传时间: 2021-09-28 21:34:47 | 文件大小: 68KB | 文件类型: ZIP
riscv-simple-sv 这是用于教学目的的简单RISC V(rv32i)内核的集合。 它们是用SystemVerilog的子集编写的,是开源硬件综合框架和理解的, 是C ++编译器的开源Verilog。 该实现非常简单,没有麻烦,并且已明智地进行了模块化,因此综合工具生成的原理图是可读的。 当前实现了三个核心: 单周期内核(每个周期一条指令,单独的指令和数据总线), 多周期内核(每条指令多个周期,一条存储器总线,一个加法器), 流水线核心(五级流水线)。 单周期内核改编自 。 已对代码结构进行了修改,以提高可读性,并修复了一些错误。 测验 核心使用。

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