cpu.zip（5级流水线结构的CPU实现）
一个 5 级流水线结构的简单 CPU的实现。TinyMIPS 的流水线共分为五级，对应五个功能模块，分别为 IF（取指令）、ID（译码）、 EX（执行）、MEM（访存）、WB（写回）。而这五个流水级分别对应 CPU 处理指令时的 五个步骤：IF 级负责从存储器（内存或缓存）中取出指令；ID 级负责将指令译码，并从寄 存器堆取出指令的操作数；EX 级负责根据译码结果执行对应的 ALU 操作；MEM 级负责处 理可能产生访存请求的指令，向存储器（内存或缓存）发送控制信号；WB 级负责将指令的 执行结果写回寄存器堆。
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