verilog单周期CPU设计

[{"title":"（ 12 个子文件 7KB ） verilog单周期CPU设计","children":[{"title":"qlz","children":[{"title":"ALU.v <span style='color:#111;'> 1.02KB </span>","children":null,"spread":false},{"title":"SH.v <span style='color:#111;'> 766B </span>","children":null,"spread":false},{"title":"EXT.v <span style='color:#111;'> 687B </span>","children":null,"spread":false},{"title":"lh.v <span style='color:#111;'> 807B </span>","children":null,"spread":false},{"title":"im_4k.v <span style='color:#111;'> 1.10KB </span>","children":null,"spread":false},{"title":"mips.v <span style='color:#111;'> 3.47KB </span>","children":null,"spread":false},{"title":"PCcal.v <span style='color:#111;'> 934B </span>","children":null,"spread":false},{"title":"control.v <span style='color:#111;'> 4.31KB </span>","children":null,"spread":false},{"title":"dm_4k.v <span style='color:#111;'> 1.08KB </span>","children":null,"spread":false},{"title":"pc.v <span style='color:#111;'> 746B </span>","children":null,"spread":false},{"title":"GRF.v <span style='color:#111;'> 1.07KB </span>","children":null,"spread":false},{"title":"mutiplexer.v <span style='color:#111;'> 1.26KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]