[{"title":"( 4 个子文件 1.86MB ) 基于FPGA设计的DSCope便携开源示波器电路设计项目源文件-电路方案","children":[{"title":"DSLogic-hdl-master.zip <span style='color:#111;'> 248.09KB </span>","children":null,"spread":false},{"title":"FsCrEFsNXvvIfLD_OZ7pvvJp8Oh8.png <span style='color:#111;'> 261.88KB </span>","children":null,"spread":false},{"title":"新建文件夹.zip <span style='color:#111;'> 263.88KB </span>","children":null,"spread":false},{"title":"新建文件夹 (2).zip <span style='color:#111;'> 1.11MB </span>","children":null,"spread":false}],"spread":true}]