加法器MATLAB代码-ASPP_HW:用于完全卷积网络的多Kong空间金字塔池(ASPP)的SoC实现

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加法器MATLAB代码用于全卷积网络的 Atrous 空间金字塔池的 SoC 实现 队号 xohw19-188 项目名 用于全卷积网络的 Atrous 空间金字塔池的 SoC 实现 日期 2019 年 6 月 27 日。 上传档案的版本 1 大学名称 卡拉布里亚大学 信息学、建模、电子和系统工程系 主管姓名 斯蒂芬妮娅·佩里 主管邮箱 参与者 克里斯蒂安·塞斯蒂托 电子邮件 使用的板 Digilent ZedBoard Zynq-7000 ARM/FPGA SoC 开发板 Vivado 版本 2017.4 项目简述 此设计提供了一种新颖的 IP 核,该核采用 Atrous 空间金字塔池化方法,以更好地执行用于深度学习目的的语义图像分割。 通过以不同的速率应用扩张卷积,研究人员已经表明,这种策略可以更好地管理视野,并能够更好地识别多个尺度的物体。 通过利用 FPGA 的并行化能力,联合执行多个扩张卷积和全局平均池化。 通过使用 ZedBoard,整个系统允许内核和 DDR 之间通过 DMA 进行通信; 这些测试旨在通过​​将组件提供并存储在 DDR 中的结果与模拟其行为的 MATLAB

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