[{"title":"( 233 个子文件 859KB ) VHDL 数字钟 简易信号发生器设计与实现","children":[{"title":"wavegen.pin <span style='color:#111;'> 12.63KB </span>","children":null,"spread":false},{"title":"wavegen.pof <span style='color:#111;'> 7.81KB </span>","children":null,"spread":false},{"title":"wavegen.vhd <span style='color:#111;'> 6.50KB </span>","children":null,"spread":false},{"title":"wavegen.(11).cnf.hdb <span style='color:#111;'> 1.10KB </span>","children":null,"spread":false},{"title":"wavegen.(19).cnf.cdb <span style='color:#111;'> 743B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]