Verilog FPGA 交通灯 设计（基于Basys2设计，使用者只需移植到板子上即可使用，三段式状态机编写）

[{"title":"（ 127 个子文件 770KB ） Verilog FPGA 交通灯 设计（基于Basys2设计，使用者只需移植到板子上即可使用，三段式状态机编写）","children":[{"title":"fuse.xmsgs <span style='color:#111;'> 367B </span>","children":null,"spread":false},{"title":"planAhead_pid6348.debug <span style='color:#111;'> 3.70KB </span>","children":null,"spread":false},{"title":"test_top_isim_beh.exe <span style='color:#111;'> 92.50KB </span>","children":null,"spread":false},{"title":"xilinxsim.ini <span style='color:#111;'> 16B </span>","children":null,"spread":false},{"title":"isim.log <span style='color:#111;'> 837B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]