[{"title":"( 6 个子文件 61.36MB ) systemverilog.rar","children":[{"title":"systemverilog","children":[{"title":"RTL级代码编写.rar <span style='color:#111;'> 9.59MB </span>","children":null,"spread":false},{"title":"VerilogHDL硬件描述语言.pdf <span style='color:#111;'> 4.74MB </span>","children":null,"spread":false},{"title":"SystemVerilog_3.1a.doc <span style='color:#111;'> 21.68MB </span>","children":null,"spread":false},{"title":"SystemVerilog3.1a语言参考手册.pdf <span style='color:#111;'> 10.44MB </span>","children":null,"spread":false},{"title":"Verilog培训教材及参考例程.zip <span style='color:#111;'> 35.08MB </span>","children":null,"spread":false},{"title":"SV.zip <span style='color:#111;'> 2.98MB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]