[{"title":"( 6 个子文件 6KB ) 串口通信程序verilog实现","children":[{"title":"verilog uart","children":[{"title":"uart_top.v <span style='color:#111;'> 1.76KB </span>","children":null,"spread":false},{"title":"uart_tx.v <span style='color:#111;'> 4.69KB </span>","children":null,"spread":false},{"title":"uart_tb.v <span style='color:#111;'> 3.35KB </span>","children":null,"spread":false},{"title":"BaudRate.v <span style='color:#111;'> 1.36KB </span>","children":null,"spread":false},{"title":"uart_rx.v <span style='color:#111;'> 3.94KB </span>","children":null,"spread":false},{"title":"top.v <span style='color:#111;'> 1.47KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]