[{"title":"( 2 个子文件 32.01MB ) HDL Chip Design","children":[{"title":"HDL Chip Design","children":[{"title":"新建 文本文档.txt <span style='color:#111;'> 162B </span>","children":null,"spread":false},{"title":"A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.pdf <span style='color:#111;'> 38.75MB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]