FPGA实现以太网IP核

[{"title":"（ 53 个子文件 825KB ） FPGA实现以太网IP核","children":[{"title":"ethernet","children":[{"title":"rtl","children":[{"title":"verilog","children":[{"title":"eth_wishbone.v <span style='color:#111;'> 70.59KB </span>","children":null,"spread":false},{"title":"BUGS <span style='color:#111;'> 3.26KB </span>","children":null,"spread":false},{"title":"eth_transmitcontrol.v <span style='color:#111;'> 11.12KB </span>","children":null,"spread":false},{"title":"eth_fifo.v <span style='color:#111;'> 5.96KB </span>","children":null,"spread":false},{"title":"TODO <span style='color:#111;'> 3.96KB </span>","children":null,"spread":false},{"title":"eth_crc.v <span style='color:#111;'> 7.48KB </span>","children":null,"spread":false},{"title":"eth_spram_256x32.v <span style='color:#111;'> 6.82KB </span>","children":null,"spread":false},{"title":"eth_rxethmac.v <span style='color:#111;'> 13.39KB </span>","children":null,"spread":false},{"title":"eth_top.v <span style='color:#111;'> 34.83KB </span>","children":null,"spread":false},{"title":"eth_maccontrol.v <span style='color:#111;'> 12.08KB </span>","children":null,"spread":false},{"title":"eth_cop.v <span style='color:#111;'> 13.43KB </span>","children":null,"spread":false},{"title":"eth_defines.v <span style='color:#111;'> 11.99KB </span>","children":null,"spread":false},{"title":"eth_outputcontrol.v <span style='color:#111;'> 6.51KB </span>","children":null,"spread":false},{"title":"eth_txstatem.v <span style='color:#111;'> 10.55KB </span>","children":null,"spread":false},{"title":"eth_rxcounters.v <span style='color:#111;'> 8.62KB </span>","children":null,"spread":false},{"title":"eth_rxstatem.v <span style='color:#111;'> 7.68KB </span>","children":null,"spread":false},{"title":"eth_register.v <span style='color:#111;'> 4.85KB </span>","children":null,"spread":false},{"title":"eth_receivecontrol.v <span style='color:#111;'> 14.41KB </span>","children":null,"spread":false},{"title":"eth_shiftreg.v <span style='color:#111;'> 6.93KB </span>","children":null,"spread":false},{"title":"eth_miim.v <span style='color:#111;'> 16.31KB </span>","children":null,"spread":false},{"title":"timescale.v <span style='color:#111;'> 3.29KB </span>","children":null,"spread":false},{"title":"eth_txethmac.v <span style='color:#111;'> 17.63KB </span>","children":null,"spread":false},{"title":"eth_rxaddrcheck.v <span style='color:#111;'> 7.45KB </span>","children":null,"spread":false},{"title":"nLint.rc <span style='color:#111;'> 3.93KB </span>","children":null,"spread":false},{"title":"eth_random.v <span style='color:#111;'> 6.14KB </span>","children":null,"spread":false},{"title":"eth_clockgen.v <span style='color:#111;'> 5.70KB </span>","children":null,"spread":false},{"title":"eth_txcounters.v <span style='color:#111;'> 9.05KB </span>","children":null,"spread":false},{"title":"eth_macstatus.v <span style='color:#111;'> 12.58KB </span>","children":null,"spread":false},{"title":"eth_registers.v <span style='color:#111;'> 28.21KB </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"doc","children":[{"title":"eth_speci.pdf <span style='color:#111;'> 248.10KB </span>","children":null,"spread":false},{"title":"src","children":[{"title":"eth_speci.doc <span style='color:#111;'> 553.50KB </span>","children":null,"spread":false},{"title":"eth_design_document.doc <span style='color:#111;'> 416.50KB </span>","children":null,"spread":false},{"title":"ethernet_product_brief_OC_head.doc <span style='color:#111;'> 153.50KB </span>","children":null,"spread":false},{"title":"ethernet_datasheet_OC_head.doc <span style='color:#111;'> 170.50KB </span>","children":null,"spread":false}],"spread":true},{"title":"eth_design_document.pdf <span style='color:#111;'> 158.97KB </span>","children":null,"spread":false},{"title":"ethernet_product_brief_OC_head.pdf <span style='color:#111;'> 19.44KB </span>","children":null,"spread":false},{"title":"ethernet_datasheet_OC_head.pdf <span style='color:#111;'> 19.70KB </span>","children":null,"spread":false}],"spread":true},{"title":"bench","children":[{"title":"verilog","children":[{"title":"tb_ethernet_with_cop.v <span style='color:#111;'> 20.05KB </span>","children":null,"spread":false},{"title":"tb_eth_defines.v <span style='color:#111;'> 11.01KB </span>","children":null,"spread":false},{"title":"wb_master_behavioral.v <span style='color:#111;'> 23.87KB </span>","children":null,"spread":false},{"title":"eth_memory.v <span style='color:#111;'> 6.29KB </span>","children":null,"spread":false},{"title":"eth_host.v <span style='color:#111;'> 5.09KB </span>","children":null,"spread":false},{"title":"wb_model_defines.v <span style='color:#111;'> 7.51KB </span>","children":null,"spread":false},{"title":"wb_slave_behavioral.v <span style='color:#111;'> 12.65KB </span>","children":null,"spread":false},{"title":"tb_ethernet.v <span style='color:#111;'> 764.51KB </span>","children":null,"spread":false},{"title":"eth_phy_defines.v <span style='color:#111;'> 4.76KB </span>","children":null,"spread":false},{"title":"tb_cop.v <span style='color:#111;'> 14.10KB </span>","children":null,"spread":false},{"title":"wb_bus_mon.v <span style='color:#111;'> 16.97KB </span>","children":null,"spread":false},{"title":"tb_eth_top.v <span style='color:#111;'> 52.15KB </span>","children":null,"spread":false},{"title":"eth_phy.v <span style='color:#111;'> 42.26KB </span>","children":null,"spread":false},{"title":"wb_master32.v <span style='color:#111;'> 13.91KB </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"README.txt <span style='color:#111;'> 4.83KB </span>","children":null,"spread":false},{"title":"ethernet.companion <span style='color:#111;'> 2.31KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]