[{"title":"( 301 个子文件 21.17MB ) 基于Nexys4 DDR的FPGA串口模块,带缓冲FIFO","children":[{"title":"vivado_5760.backup.log <span style='color:#111;'> 5.44KB </span>","children":null,"spread":false},{"title":"vivado_5760.backup.jou <span style='color:#111;'> 1.52KB </span>","children":null,"spread":false},{"title":"vivado.jou <span style='color:#111;'> 1.55KB </span>","children":null,"spread":false},{"title":"vivado_4300.backup.log <span style='color:#111;'> 6.71KB </span>","children":null,"spread":false},{"title":"uart_TB.v <span style='color:#111;'> 1.60KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]