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[{"title":"（ 82 个子文件 49.73MB ） 赛灵思FPGA集成库，包含最新的7系列，Altium designer版本","children":[{"title":"Xilinx","children":[{"title":"Xilinx Automotive IQ.IntLib <span style='color:#111;'> 214.50KB </span>","children":null,"spread":false},{"title":"Xilinx XC9500 FPGA.IntLib <span style='color:#111;'> 95.00KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-3AN.IntLib <span style='color:#111;'> 205.50KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-E FPGA.IntLib <span style='color:#111;'> 140.50KB </span>","children":null,"spread":false},{"title":"Xilinx XC9500XV FPGA.IntLib <span style='color:#111;'> 94.50KB </span>","children":null,"spread":false},{"title":"Xilinx XC4000XL.IntLib <span style='color:#111;'> 879.00KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan XL.IntLib <span style='color:#111;'> 124.50KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-II.IntLib <span style='color:#111;'> 2.08MB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-II Pro FPGA.IntLib <span style='color:#111;'> 235.00KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex.IntLib <span style='color:#111;'> 674.00KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-II FPGA.IntLib <span style='color:#111;'> 137.50KB </span>","children":null,"spread":false},{"title":"Xilinx XC4000E.IntLib <span style='color:#111;'> 424.50KB </span>","children":null,"spread":false},{"title":"Xilinx Aerospace and Defense.IntLib <span style='color:#111;'> 1.28MB </span>","children":null,"spread":false},{"title":"Xilinx XCF.IntLib <span style='color:#111;'> 35.00KB </span>","children":null,"spread":false},{"title":"Xilinx XC17S00.IntLib <span style='color:#111;'> 40.00KB </span>","children":null,"spread":false},{"title":"Xilinx CoolRunner II.IntLib <span style='color:#111;'> 589.50KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-4.IntLib <span style='color:#111;'> 2.82MB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-3E FPGA.IntLib <span style='color:#111;'> 138.50KB </span>","children":null,"spread":false},{"title":"Xilinx XA9500XL FPGA.IntLib <span style='color:#111;'> 94.50KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-3A FPGA.IntLib <span style='color:#111;'> 131.50KB </span>","children":null,"spread":false},{"title":"Xilinx XA CoolRunner II.IntLib <span style='color:#111;'> 54.50KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan3E FPGA.IntLib <span style='color:#111;'> 112.50KB </span>","children":null,"spread":false},{"title":"Xilinx XASpartan-3A FPGA.IntLib <span style='color:#111;'> 131.50KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-II Pro.IntLib <span style='color:#111;'> 4.12MB </span>","children":null,"spread":false},{"title":"Xilinx XA Spartan-3A.IntLib <span style='color:#111;'> 87.50KB </span>","children":null,"spread":false},{"title":"Xilinx XC1700E.IntLib <span style='color:#111;'> 46.50KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-7.IntLib <span style='color:#111;'> 2.27MB </span>","children":null,"spread":false},{"title":"Xilinx XA Spartan-3E.IntLib <span style='color:#111;'> 87.00KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-5 FPGA.IntLib <span style='color:#111;'> 58.50KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-4 FPGA.IntLib <span style='color:#111;'> 138.00KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-3.IntLib <span style='color:#111;'> 1.61MB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-II Pro X.IntLib <span style='color:#111;'> 323.50KB </span>","children":null,"spread":false},{"title":"Xilinx XA9500XL.IntLib <span style='color:#111;'> 37.00KB </span>","children":null,"spread":false},{"title":"Xilinx XC9500.IntLib <span style='color:#111;'> 504.50KB </span>","children":null,"spread":false},{"title":"Xilinx XASpartan3E FPGA.IntLib <span style='color:#111;'> 112.50KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-IIE.IntLib <span style='color:#111;'> 359.00KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-3A DSP.IntLib <span style='color:#111;'> 153.50KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-6 FPGA.IntLib <span style='color:#111;'> 144.00KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-6 FPGA.IntLib <span style='color:#111;'> 146.00KB </span>","children":null,"spread":false},{"title":"Xilinx Memory SPROM.IntLib <span style='color:#111;'> 220.00KB </span>","children":null,"spread":false},{"title":"Xilinx XC3000.IntLib <span style='color:#111;'> 1.57MB </span>","children":null,"spread":false},{"title":"Xilinx CoolRunner-II FPGA.IntLib <span style='color:#111;'> 115.50KB </span>","children":null,"spread":false},{"title":"Xilinx Footprints.PcbLib <span style='color:#111;'> 11.01MB </span>","children":null,"spread":false},{"title":"Xilinx XC18V00.IntLib <span style='color:#111;'> 37.00KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-6L-2.IntLib <span style='color:#111;'> 783.50KB </span>","children":null,"spread":false},{"title":"Xilinx Zynq-7000.IntLib <span style='color:#111;'> 294.00KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-3L.IntLib <span style='color:#111;'> 190.50KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-3ADSP FPGA.IntLib <span style='color:#111;'> 131.50KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-II.IntLib <span style='color:#111;'> 251.50KB </span>","children":null,"spread":false},{"title":"Xilinx XC7000.IntLib <span style='color:#111;'> 391.50KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-3E.IntLib <span style='color:#111;'> 314.50KB </span>","children":null,"spread":false},{"title":"Xilinx XC4000EX.IntLib <span style='color:#111;'> 154.50KB </span>","children":null,"spread":false},{"title":"Xilinx Kintex-7.IntLib <span style='color:#111;'> 892.50KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex FPGA.IntLib <span style='color:#111;'> 137.50KB </span>","children":null,"spread":false},{"title":"Xilinx XC4000XLA.IntLib <span style='color:#111;'> 445.00KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-6.IntLib <span style='color:#111;'> 4.46MB </span>","children":null,"spread":false},{"title":"Xilinx XA Spartan-3A DSP.IntLib <span style='color:#111;'> 53.00KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-6L.IntLib <span style='color:#111;'> 802.00KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-E.IntLib <span style='color:#111;'> 1.65MB </span>","children":null,"spread":false},{"title":"Xilinx CoolRunner-XPLA3 FPGA.IntLib <span style='color:#111;'> 94.00KB </span>","children":null,"spread":false},{"title":"Xilinx XC5200.IntLib <span style='color:#111;'> 368.50KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan.IntLib <span style='color:#111;'> 99.50KB </span>","children":null,"spread":false},{"title":"Xilinx CoolRunner XPLA3.IntLib <span style='color:#111;'> 825.50KB </span>","children":null,"spread":false},{"title":"Xilinx Artix-7.IntLib <span style='color:#111;'> 433.00KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-5.IntLib <span style='color:#111;'> 5.27MB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-IIE FPGA.IntLib <span style='color:#111;'> 141.50KB </span>","children":null,"spread":false},{"title":"Xilinx XC4000.IntLib <span style='color:#111;'> 1.12MB </span>","children":null,"spread":false},{"title":"Xilinx XC9500XL.IntLib <span style='color:#111;'> 489.50KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-6-2.IntLib <span style='color:#111;'> 4.35MB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-3 FPGA.IntLib <span style='color:#111;'> 243.50KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan-3A.IntLib <span style='color:#111;'> 423.50KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-II FPGA.IntLib <span style='color:#111;'> 241.00KB </span>","children":null,"spread":false},{"title":"Xilinx XC2000.IntLib <span style='color:#111;'> 171.00KB </span>","children":null,"spread":false},{"title":"Xilinx XASpartan-3ADSP FPGA.IntLib <span style='color:#111;'> 131.50KB </span>","children":null,"spread":false},{"title":"Xilinx XC17V00.IntLib <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-6.IntLib <span style='color:#111;'> 6.68MB </span>","children":null,"spread":false},{"title":"Xilinx Virtex-II Pro X FPGA.IntLib <span style='color:#111;'> 235.00KB </span>","children":null,"spread":false},{"title":"Xilinx XC9500XL FPGA.IntLib <span style='color:#111;'> 94.50KB </span>","children":null,"spread":false},{"title":"Xilinx Spartan FPGA.IntLib <span style='color:#111;'> 106.00KB </span>","children":null,"spread":false},{"title":"Xilinx XC17S00A.IntLib <span style='color:#111;'> 37.00KB </span>","children":null,"spread":false},{"title":"Xilinx XC9500XV.IntLib <span style='color:#111;'> 195.00KB </span>","children":null,"spread":false},{"title":"Xilinx XC1700.IntLib <span style='color:#111;'> 35.00KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]
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本站所有资源不代表本站的观点或立场，基于网友分享，根据中国法律《信息网络传播权保护条例》第二十二条之规定，若资源存在侵权或相关问题请联系本站客服人员，zhiweidada#qq.com，请把#换成@，本站将给予最大的支持与配合，做到及时反馈和处理。关于更多版权及免责申明参见 版权及免责申明