[{"title":"( 11 个子文件 9KB ) 16位单周期cpu的verilog实现","children":[{"title":"sccpu","children":[{"title":"top_module.v <span style='color:#111;'> 1.46KB </span>","children":null,"spread":false},{"title":"cpu_test.v <span style='color:#111;'> 1.69KB </span>","children":null,"spread":false},{"title":"seg7_controller.v <span style='color:#111;'> 2.15KB </span>","children":null,"spread":false},{"title":"data_mem.v <span style='color:#111;'> 1.08KB </span>","children":null,"spread":false},{"title":"i_memory.v <span style='color:#111;'> 2.30KB </span>","children":null,"spread":false},{"title":"instru_mem.v <span style='color:#111;'> 2.29KB </span>","children":null,"spread":false},{"title":"cpu.v <span style='color:#111;'> 6.83KB </span>","children":null,"spread":false},{"title":"clk_divider.v <span style='color:#111;'> 863B </span>","children":null,"spread":false},{"title":"maindec.v <span style='color:#111;'> 2.74KB </span>","children":null,"spread":false},{"title":"controller.v <span style='color:#111;'> 874B </span>","children":null,"spread":false},{"title":"aludec.v <span style='color:#111;'> 588B </span>","children":null,"spread":false}],"spread":false}],"spread":true}]