XILINX FPGA双通道的12bit ADC ad9226输入测试程序VERILOG逻辑源码 ISE14.7工程

上传者: skcqtgzx | 上传时间: 2023-12-07 20:36:32 | 文件大小: 2.31MB | 文件类型: RAR
XILINX SPARTAN6 FPGA 双通道的12bit ADC ad9226输入测试程序VERILOG逻辑例程源码 ISE14.7工程文件 module ad9226_test( input clk50m, input reset_n, input rx, //uart rx output tx, //uart tx input [11:0] ad1_in, output ad1_clk, input [11:0] ad2_in, output ad2_clk ); parameter SCOPE_DIV =50; //定义chipscoe的分频系数, assign ad1_clk=clk50m; assign ad2_clk=clk50m; wire [11:0] ad_ch1; wire [11:0] ad_ch2; wire [7:0] ch1_sig; w

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